a5a56871f8
Exynos7 I2S controller has no internal dma, supports more no. of root clock sampling frequencies and has more no.of Rx fifos to support 7.1CH recording in TDM mode. Due to more no. of root clock frequency values some of the bit offsets got shifted up by one. Also I2S1 on previous Samsung platforms uses v3 dai type but on Exynos7 it is upgraded to v5 with slightly modified register offsets for supporting more no.of RFS values. Due to the above changes, the driver has to be modified to handle all versions of I2S controller. For this I introduced a new structure to hold modified bit offsets and masks which is passed as dai data. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
165 lines
4.5 KiB
C
165 lines
4.5 KiB
C
/*
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* linux/sound/soc/samsung/i2s-regs.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung I2S driver's register header
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __SND_SOC_SAMSUNG_I2S_REGS_H
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#define __SND_SOC_SAMSUNG_I2S_REGS_H
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#define I2SCON 0x0
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#define I2SMOD 0x4
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#define I2SFIC 0x8
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#define I2SPSR 0xc
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#define I2STXD 0x10
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#define I2SRXD 0x14
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#define I2SFICS 0x18
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#define I2STXDS 0x1c
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#define I2SAHB 0x20
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#define I2SSTR0 0x24
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#define I2SSIZE 0x28
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#define I2STRNCNT 0x2c
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#define I2SLVL0ADDR 0x30
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#define I2SLVL1ADDR 0x34
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#define I2SLVL2ADDR 0x38
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#define I2SLVL3ADDR 0x3c
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#define I2SSTR1 0x40
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#define I2SVER 0x44
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#define I2SFIC1 0x48
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#define I2STDM 0x4c
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#define I2SFSTA 0x50
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#define CON_RSTCLR (1 << 31)
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#define CON_FRXOFSTATUS (1 << 26)
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#define CON_FRXORINTEN (1 << 25)
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#define CON_FTXSURSTAT (1 << 24)
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#define CON_FTXSURINTEN (1 << 23)
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#define CON_TXSDMA_PAUSE (1 << 20)
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#define CON_TXSDMA_ACTIVE (1 << 18)
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#define CON_FTXURSTATUS (1 << 17)
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#define CON_FTXURINTEN (1 << 16)
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#define CON_TXFIFO2_EMPTY (1 << 15)
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#define CON_TXFIFO1_EMPTY (1 << 14)
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#define CON_TXFIFO2_FULL (1 << 13)
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#define CON_TXFIFO1_FULL (1 << 12)
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#define CON_LRINDEX (1 << 11)
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#define CON_TXFIFO_EMPTY (1 << 10)
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#define CON_RXFIFO_EMPTY (1 << 9)
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#define CON_TXFIFO_FULL (1 << 8)
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#define CON_RXFIFO_FULL (1 << 7)
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#define CON_TXDMA_PAUSE (1 << 6)
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#define CON_RXDMA_PAUSE (1 << 5)
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#define CON_TXCH_PAUSE (1 << 4)
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#define CON_RXCH_PAUSE (1 << 3)
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#define CON_TXDMA_ACTIVE (1 << 2)
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#define CON_RXDMA_ACTIVE (1 << 1)
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#define CON_ACTIVE (1 << 0)
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#define MOD_OPCLK_CDCLK_OUT (0 << 30)
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#define MOD_OPCLK_CDCLK_IN (1 << 30)
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#define MOD_OPCLK_BCLK_OUT (2 << 30)
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#define MOD_OPCLK_PCLK (3 << 30)
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#define MOD_OPCLK_MASK (3 << 30)
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#define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */
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#define MOD_BLCS_SHIFT 26
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#define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT)
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#define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT)
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#define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT)
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#define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT)
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#define MOD_BLCP_SHIFT 24
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#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
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#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
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#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
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#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
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#define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */
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#define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */
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#define MOD_C1DD_HHALF (1 << 19)
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#define MOD_C1DD_LHALF (1 << 18)
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#define MOD_DC2_EN (1 << 17)
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#define MOD_DC1_EN (1 << 16)
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#define MOD_BLC_16BIT (0 << 13)
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#define MOD_BLC_8BIT (1 << 13)
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#define MOD_BLC_24BIT (2 << 13)
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#define MOD_BLC_MASK (3 << 13)
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#define MOD_TXONLY (0 << 8)
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#define MOD_RXONLY (1 << 8)
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#define MOD_TXRX (2 << 8)
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#define MOD_MASK (3 << 8)
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#define MOD_LRP_SHIFT 7
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#define MOD_LR_LLOW 0
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#define MOD_LR_RLOW 1
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#define MOD_SDF_SHIFT 5
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#define MOD_SDF_IIS 0
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#define MOD_SDF_MSB 1
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#define MOD_SDF_LSB 2
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#define MOD_SDF_MASK 3
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#define MOD_RCLK_SHIFT 3
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#define MOD_RCLK_256FS 0
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#define MOD_RCLK_512FS 1
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#define MOD_RCLK_384FS 2
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#define MOD_RCLK_768FS 3
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#define MOD_RCLK_MASK 3
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#define MOD_BCLK_SHIFT 1
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#define MOD_BCLK_32FS 0
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#define MOD_BCLK_48FS 1
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#define MOD_BCLK_16FS 2
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#define MOD_BCLK_24FS 3
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#define MOD_BCLK_MASK 3
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#define MOD_8BIT (1 << 0)
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#define EXYNOS5420_MOD_LRP_SHIFT 15
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#define EXYNOS5420_MOD_SDF_SHIFT 6
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#define EXYNOS5420_MOD_RCLK_SHIFT 4
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#define EXYNOS5420_MOD_BCLK_SHIFT 0
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#define EXYNOS5420_MOD_BCLK_64FS 4
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#define EXYNOS5420_MOD_BCLK_96FS 5
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#define EXYNOS5420_MOD_BCLK_128FS 6
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#define EXYNOS5420_MOD_BCLK_192FS 7
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#define EXYNOS5420_MOD_BCLK_256FS 8
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#define EXYNOS5420_MOD_BCLK_MASK 0xf
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#define EXYNOS7_MOD_RCLK_64FS 4
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#define EXYNOS7_MOD_RCLK_128FS 5
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#define EXYNOS7_MOD_RCLK_96FS 6
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#define EXYNOS7_MOD_RCLK_192FS 7
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#define PSR_PSREN (1 << 15)
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#define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
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#define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
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#define FIC_TXFLUSH (1 << 15)
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#define FIC_RXFLUSH (1 << 7)
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#define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
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#define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
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#define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
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#define AHB_INTENLVL0 (1 << 24)
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#define AHB_LVL0INT (1 << 20)
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#define AHB_CLRLVL0INT (1 << 16)
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#define AHB_DMARLD (1 << 5)
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#define AHB_INTMASK (1 << 3)
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#define AHB_DMAEN (1 << 0)
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#define AHB_LVLINTMASK (0xf << 20)
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#define I2SSIZE_TRNMSK (0xffff)
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#define I2SSIZE_SHIFT (16)
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#endif /* __SND_SOC_SAMSUNG_I2S_REGS_H */
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