![Tejun Heo](/assets/img/avatar_default.png)
VIA controllers clear DEVICE register when IEN changes. Make sure DEVICE is updated along with CTL. This change is separated from Joseph Chan's larger patch. http://thread.gmane.org/gmane.linux.kernel.commits.mm/40640 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Joseph Chan <JosephChan@via.com.tw> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
496 lines
13 KiB
C
496 lines
13 KiB
C
/*
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* sata_via.c - VIA Serial ATA controllers
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2004 Red Hat, Inc. All rights reserved.
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* Copyright 2003-2004 Jeff Garzik
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available under NDA.
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*
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*
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_via"
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#define DRV_VERSION "2.3"
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enum board_ids_enum {
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vt6420,
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vt6421,
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};
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enum {
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SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
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SATA_INT_GATE = 0x41, /* SATA interrupt gating */
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SATA_NATIVE_MODE = 0x42, /* Native mode enable */
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PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
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PATA_PIO_TIMING = 0xAB, /* PATA timing register */
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PORT0 = (1 << 1),
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PORT1 = (1 << 0),
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ALL_PORTS = PORT0 | PORT1,
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NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),
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SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
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};
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static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
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static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
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static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
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static void svia_noop_freeze(struct ata_port *ap);
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static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
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static int vt6421_pata_cable_detect(struct ata_port *ap);
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static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
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static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
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static const struct pci_device_id svia_pci_tbl[] = {
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{ PCI_VDEVICE(VIA, 0x5337), vt6420 },
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{ PCI_VDEVICE(VIA, 0x0591), vt6420 },
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{ PCI_VDEVICE(VIA, 0x3149), vt6420 },
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{ PCI_VDEVICE(VIA, 0x3249), vt6421 },
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{ PCI_VDEVICE(VIA, 0x5287), vt6420 },
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{ PCI_VDEVICE(VIA, 0x5372), vt6420 },
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{ PCI_VDEVICE(VIA, 0x7372), vt6420 },
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{ } /* terminate list */
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};
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static struct pci_driver svia_pci_driver = {
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.name = DRV_NAME,
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.id_table = svia_pci_tbl,
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.probe = svia_init_one,
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#ifdef CONFIG_PM
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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.remove = ata_pci_remove_one,
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};
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static struct scsi_host_template svia_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations svia_base_ops = {
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.inherits = &ata_bmdma_port_ops,
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.sff_tf_load = svia_tf_load,
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};
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static struct ata_port_operations vt6420_sata_ops = {
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.inherits = &svia_base_ops,
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.freeze = svia_noop_freeze,
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.prereset = vt6420_prereset,
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};
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static struct ata_port_operations vt6421_pata_ops = {
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.inherits = &svia_base_ops,
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.cable_detect = vt6421_pata_cable_detect,
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.set_piomode = vt6421_set_pio_mode,
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.set_dmamode = vt6421_set_dma_mode,
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};
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static struct ata_port_operations vt6421_sata_ops = {
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.inherits = &svia_base_ops,
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.scr_read = svia_scr_read,
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.scr_write = svia_scr_write,
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};
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static const struct ata_port_info vt6420_port_info = {
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA6,
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.port_ops = &vt6420_sata_ops,
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};
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static struct ata_port_info vt6421_sport_info = {
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA6,
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.port_ops = &vt6421_sata_ops,
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};
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static struct ata_port_info vt6421_pport_info = {
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_LEGACY,
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.pio_mask = 0x1f,
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.mwdma_mask = 0,
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.udma_mask = ATA_UDMA6,
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.port_ops = &vt6421_pata_ops,
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};
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MODULE_AUTHOR("Jeff Garzik");
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MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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*val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg));
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return 0;
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}
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static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg));
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return 0;
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}
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/**
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* svia_tf_load - send taskfile registers to host controller
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* @ap: Port to which output is sent
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* @tf: ATA taskfile register set
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*
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* Outputs ATA taskfile to standard ATA host controller.
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*
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* This is to fix the internal bug of via chipsets, which will
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* reset the device register after changing the IEN bit on ctl
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* register.
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*/
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static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_taskfile ttf;
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if (tf->ctl != ap->last_ctl) {
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ttf = *tf;
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ttf.flags |= ATA_TFLAG_DEVICE;
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tf = &ttf;
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}
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ata_sff_tf_load(ap, tf);
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}
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static void svia_noop_freeze(struct ata_port *ap)
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{
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/* Some VIA controllers choke if ATA_NIEN is manipulated in
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* certain way. Leave it alone and just clear pending IRQ.
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*/
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ap->ops->sff_check_status(ap);
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ata_sff_irq_clear(ap);
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}
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/**
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* vt6420_prereset - prereset for vt6420
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* @link: target ATA link
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* @deadline: deadline jiffies for the operation
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*
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* SCR registers on vt6420 are pieces of shit and may hang the
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* whole machine completely if accessed with the wrong timing.
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* To avoid such catastrophe, vt6420 doesn't provide generic SCR
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* access operations, but uses SStatus and SControl only during
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* boot probing in controlled way.
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*
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* As the old (pre EH update) probing code is proven to work, we
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* strictly follow the access pattern.
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*
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* LOCKING:
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* Kernel thread context (may sleep)
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*
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* RETURNS:
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* 0 on success, -errno otherwise.
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*/
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static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct ata_eh_context *ehc = &ap->link.eh_context;
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unsigned long timeout = jiffies + (HZ * 5);
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u32 sstatus, scontrol;
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int online;
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/* don't do any SCR stuff if we're not loading */
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if (!(ap->pflags & ATA_PFLAG_LOADING))
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goto skip_scr;
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/* Resume phy. This is the old SATA resume sequence */
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svia_scr_write(link, SCR_CONTROL, 0x300);
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svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */
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/* wait for phy to become ready, if necessary */
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do {
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msleep(200);
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svia_scr_read(link, SCR_STATUS, &sstatus);
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if ((sstatus & 0xf) != 1)
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break;
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} while (time_before(jiffies, timeout));
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/* open code sata_print_link_status() */
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svia_scr_read(link, SCR_STATUS, &sstatus);
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svia_scr_read(link, SCR_CONTROL, &scontrol);
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online = (sstatus & 0xf) == 0x3;
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ata_port_printk(ap, KERN_INFO,
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"SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
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online ? "up" : "down", sstatus, scontrol);
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/* SStatus is read one more time */
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svia_scr_read(link, SCR_STATUS, &sstatus);
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if (!online) {
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/* tell EH to bail */
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ehc->i.action &= ~ATA_EH_RESET;
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return 0;
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}
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skip_scr:
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/* wait for !BSY */
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ata_sff_wait_ready(link, deadline);
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return 0;
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}
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static int vt6421_pata_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 tmp;
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pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
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if (tmp & 0x10)
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
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pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]);
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}
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static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
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pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->dma_mode - XFER_UDMA_0]);
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}
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static const unsigned int svia_bar_sizes[] = {
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8, 4, 8, 4, 16, 256
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};
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static const unsigned int vt6421_bar_sizes[] = {
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16, 16, 16, 16, 32, 128
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};
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static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
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{
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return addr + (port * 128);
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}
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static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
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{
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return addr + (port * 64);
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}
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static void vt6421_init_addrs(struct ata_port *ap)
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{
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void __iomem * const * iomap = ap->host->iomap;
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void __iomem *reg_addr = iomap[ap->port_no];
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void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
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struct ata_ioports *ioaddr = &ap->ioaddr;
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ioaddr->cmd_addr = reg_addr;
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ioaddr->altstatus_addr =
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ioaddr->ctl_addr = (void __iomem *)
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((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
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ioaddr->bmdma_addr = bmdma_addr;
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ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
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ata_sff_std_ports(ioaddr);
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ata_port_pbar_desc(ap, ap->port_no, -1, "port");
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ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
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}
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static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
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{
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const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
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struct ata_host *host;
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int rc;
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rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
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if (rc)
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return rc;
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*r_host = host;
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rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
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if (rc) {
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dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n");
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return rc;
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}
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host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
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host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
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return 0;
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}
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static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
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{
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const struct ata_port_info *ppi[] =
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{ &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
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struct ata_host *host;
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int i, rc;
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*r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
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if (!host) {
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dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
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return -ENOMEM;
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}
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rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
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if (rc) {
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dev_printk(KERN_ERR, &pdev->dev, "failed to request/iomap "
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"PCI BARs (errno=%d)\n", rc);
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return rc;
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}
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host->iomap = pcim_iomap_table(pdev);
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for (i = 0; i < host->n_ports; i++)
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vt6421_init_addrs(host->ports[i]);
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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return 0;
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}
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static void svia_configure(struct pci_dev *pdev)
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{
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u8 tmp8;
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pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
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dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n",
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(int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
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/* make sure SATA channels are enabled */
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pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
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if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
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dev_printk(KERN_DEBUG, &pdev->dev,
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"enabling SATA channels (0x%x)\n",
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(int) tmp8);
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tmp8 |= ALL_PORTS;
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pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
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}
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/* make sure interrupts for each channel sent to us */
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pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
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if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
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dev_printk(KERN_DEBUG, &pdev->dev,
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"enabling SATA channel interrupts (0x%x)\n",
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(int) tmp8);
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tmp8 |= ALL_PORTS;
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pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
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}
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/* make sure native mode is enabled */
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pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
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if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
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dev_printk(KERN_DEBUG, &pdev->dev,
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"enabling SATA channel native mode (0x%x)\n",
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(int) tmp8);
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tmp8 |= NATIVE_MODE_ALL;
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pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
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}
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}
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static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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unsigned int i;
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int rc;
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struct ata_host *host;
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int board_id = (int) ent->driver_data;
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const unsigned *bar_sizes;
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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if (board_id == vt6420)
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bar_sizes = &svia_bar_sizes[0];
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else
|
|
bar_sizes = &vt6421_bar_sizes[0];
|
|
|
|
for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
|
|
if ((pci_resource_start(pdev, i) == 0) ||
|
|
(pci_resource_len(pdev, i) < bar_sizes[i])) {
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
|
|
i,
|
|
(unsigned long long)pci_resource_start(pdev, i),
|
|
(unsigned long long)pci_resource_len(pdev, i));
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (board_id == vt6420)
|
|
rc = vt6420_prepare_host(pdev, &host);
|
|
else
|
|
rc = vt6421_prepare_host(pdev, &host);
|
|
if (rc)
|
|
return rc;
|
|
|
|
svia_configure(pdev);
|
|
|
|
pci_set_master(pdev);
|
|
return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
|
|
IRQF_SHARED, &svia_sht);
|
|
}
|
|
|
|
static int __init svia_init(void)
|
|
{
|
|
return pci_register_driver(&svia_pci_driver);
|
|
}
|
|
|
|
static void __exit svia_exit(void)
|
|
{
|
|
pci_unregister_driver(&svia_pci_driver);
|
|
}
|
|
|
|
module_init(svia_init);
|
|
module_exit(svia_exit);
|