fab8ad0b2b
Add the 12 GP timers nodes present in OMAP2. Add the 12 GP timers nodes present in OMAP3. Add the 11 GP timers nodes present in OMAP4. Add the 7 GP timers nodes present in AM33xx. Add documentation for timer properties specific to OMAP. Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified Vaibhav's original nodes adding information on which timers support a PWM output. V5 changes: - Updated timer register sizes for OMAP2/3/4. - Modified AM335x timer register size to be 1KB instead of 4KB to align with HWMOD. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Acked-Reviewed-&-Tested-By: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
156 lines
3 KiB
Plaintext
156 lines
3 KiB
Plaintext
/*
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* Device Tree Source for OMAP2 SoC
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
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interrupt-parent = <&intc>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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};
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cpus {
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cpu@0 {
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compatible = "arm,arm1136jf-s";
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};
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};
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap2-mpu";
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ti,hwmods = "mpu";
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};
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};
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ocp {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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intc: interrupt-controller@1 {
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compatible = "ti,omap2-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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ti,intc-size = <96>;
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reg = <0x480FE000 0x1000>;
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};
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uart1: serial@4806a000 {
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compatible = "ti,omap2-uart";
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ti,hwmods = "uart1";
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clock-frequency = <48000000>;
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};
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uart2: serial@4806c000 {
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compatible = "ti,omap2-uart";
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ti,hwmods = "uart2";
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clock-frequency = <48000000>;
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};
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uart3: serial@4806e000 {
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compatible = "ti,omap2-uart";
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ti,hwmods = "uart3";
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clock-frequency = <48000000>;
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};
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timer2: timer@4802a000 {
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compatible = "ti,omap2-timer";
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reg = <0x4802a000 0x400>;
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interrupts = <38>;
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ti,hwmods = "timer2";
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};
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timer3: timer@48078000 {
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compatible = "ti,omap2-timer";
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reg = <0x48078000 0x400>;
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interrupts = <39>;
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ti,hwmods = "timer3";
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};
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timer4: timer@4807a000 {
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compatible = "ti,omap2-timer";
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reg = <0x4807a000 0x400>;
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interrupts = <40>;
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ti,hwmods = "timer4";
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};
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timer5: timer@4807c000 {
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compatible = "ti,omap2-timer";
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reg = <0x4807c000 0x400>;
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interrupts = <41>;
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ti,hwmods = "timer5";
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ti,timer-dsp;
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};
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timer6: timer@4807e000 {
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compatible = "ti,omap2-timer";
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reg = <0x4807e000 0x400>;
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interrupts = <42>;
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ti,hwmods = "timer6";
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ti,timer-dsp;
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};
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timer7: timer@48080000 {
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compatible = "ti,omap2-timer";
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reg = <0x48080000 0x400>;
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interrupts = <43>;
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ti,hwmods = "timer7";
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ti,timer-dsp;
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};
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timer8: timer@48082000 {
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compatible = "ti,omap2-timer";
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reg = <0x48082000 0x400>;
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interrupts = <44>;
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ti,hwmods = "timer8";
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ti,timer-dsp;
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};
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timer9: timer@48084000 {
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compatible = "ti,omap2-timer";
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reg = <0x48084000 0x400>;
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interrupts = <45>;
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ti,hwmods = "timer9";
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ti,timer-pwm;
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};
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timer10: timer@48086000 {
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compatible = "ti,omap2-timer";
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reg = <0x48086000 0x400>;
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interrupts = <46>;
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ti,hwmods = "timer10";
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ti,timer-pwm;
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};
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timer11: timer@48088000 {
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compatible = "ti,omap2-timer";
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reg = <0x48088000 0x400>;
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interrupts = <47>;
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ti,hwmods = "timer11";
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ti,timer-pwm;
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};
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timer12: timer@4808a000 {
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compatible = "ti,omap2-timer";
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reg = <0x4808a000 0x400>;
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interrupts = <48>;
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ti,hwmods = "timer12";
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ti,timer-pwm;
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};
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};
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};
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