2326669ccb
Add support for specifying clock information for the uart clk via the device tree. This eliminates the need to hardcode rates in the device tree. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
167 lines
3.7 KiB
Plaintext
167 lines
3.7 KiB
Plaintext
/*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "xlnx,zynq-7000";
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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intc: interrupt-controller@f8f01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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};
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xF8F02000 0x1000>;
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arm,data-latency = <2 3 2>;
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arm,tag-latency = <2 3 2>;
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cache-unified;
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cache-level = <2>;
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};
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uart0: uart@e0000000 {
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compatible = "xlnx,xuartps";
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reg = <0xE0000000 0x1000>;
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interrupts = <0 27 4>;
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clocks = <&uart_clk 0>;
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};
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uart1: uart@e0001000 {
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compatible = "xlnx,xuartps";
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reg = <0xE0001000 0x1000>;
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interrupts = <0 50 4>;
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clocks = <&uart_clk 1>;
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};
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slcr: slcr@f8000000 {
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compatible = "xlnx,zynq-slcr";
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reg = <0xF8000000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ps_clk: ps_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* clock-frequency set in board-specific file */
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clock-output-names = "ps_clk";
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};
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armpll: armpll {
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#clock-cells = <0>;
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compatible = "xlnx,zynq-pll";
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clocks = <&ps_clk>;
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reg = <0x100 0x110>;
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clock-output-names = "armpll";
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};
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ddrpll: ddrpll {
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#clock-cells = <0>;
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compatible = "xlnx,zynq-pll";
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clocks = <&ps_clk>;
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reg = <0x104 0x114>;
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clock-output-names = "ddrpll";
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};
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iopll: iopll {
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#clock-cells = <0>;
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compatible = "xlnx,zynq-pll";
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clocks = <&ps_clk>;
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reg = <0x108 0x118>;
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clock-output-names = "iopll";
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};
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uart_clk: uart_clk {
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#clock-cells = <1>;
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compatible = "xlnx,zynq-periph-clock";
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clocks = <&iopll &armpll &ddrpll>;
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reg = <0x154>;
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clock-output-names = "uart0_ref_clk",
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"uart1_ref_clk";
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};
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cpu_clk: cpu_clk {
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#clock-cells = <1>;
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compatible = "xlnx,zynq-cpu-clock";
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clocks = <&iopll &armpll &ddrpll>;
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reg = <0x120 0x1C4>;
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clock-output-names = "cpu_6x4x",
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"cpu_3x2x",
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"cpu_2x",
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"cpu_1x";
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};
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};
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};
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ttc0: ttc0@f8001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "xlnx,ttc";
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reg = <0xF8001000 0x1000>;
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clocks = <&cpu_clk 3>;
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clock-names = "cpu_1x";
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clock-ranges;
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ttc0_0: ttc0.0 {
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status = "disabled";
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reg = <0>;
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interrupts = <0 10 4>;
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};
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ttc0_1: ttc0.1 {
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status = "disabled";
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reg = <1>;
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interrupts = <0 11 4>;
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};
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ttc0_2: ttc0.2 {
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status = "disabled";
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reg = <2>;
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interrupts = <0 12 4>;
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};
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};
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ttc1: ttc1@f8002000 {
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#interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "xlnx,ttc";
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reg = <0xF8002000 0x1000>;
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clocks = <&cpu_clk 3>;
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clock-names = "cpu_1x";
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clock-ranges;
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ttc1_0: ttc1.0 {
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status = "disabled";
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reg = <0>;
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interrupts = <0 37 4>;
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};
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ttc1_1: ttc1.1 {
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status = "disabled";
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reg = <1>;
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interrupts = <0 38 4>;
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};
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ttc1_2: ttc1.2 {
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status = "disabled";
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reg = <2>;
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interrupts = <0 39 4>;
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};
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};
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};
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};
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