![Jesse Barnes](/assets/img/avatar_default.png)
It's possible that the CCK clock could run at a different rate than the DDR clock, so use the same method to get CCK as the GMBUS code does when calculating the new CDclk divider in the VLV display code. Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
673 lines
17 KiB
C
673 lines
17 KiB
C
/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2008,2010 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*/
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/export.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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enum disp_clk {
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CDCLK,
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CZCLK
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};
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struct gmbus_port {
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const char *name;
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int reg;
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};
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static const struct gmbus_port gmbus_ports[] = {
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{ "ssc", GPIOB },
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{ "vga", GPIOA },
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{ "panel", GPIOC },
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{ "dpc", GPIOD },
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{ "dpb", GPIOE },
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{ "dpd", GPIOF },
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};
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/* Intel GPIO access functions */
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#define I2C_RISEFALL_TIME 10
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static inline struct intel_gmbus *
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to_intel_gmbus(struct i2c_adapter *i2c)
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{
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return container_of(i2c, struct intel_gmbus, adapter);
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}
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static int get_disp_clk_div(struct drm_i915_private *dev_priv,
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enum disp_clk clk)
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{
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u32 reg_val;
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int clk_ratio;
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reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
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if (clk == CDCLK)
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clk_ratio =
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((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1;
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else
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clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1;
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return clk_ratio;
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}
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static void gmbus_set_freq(struct drm_i915_private *dev_priv)
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{
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int vco, gmbus_freq = 0, cdclk_div;
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BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
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vco = valleyview_get_vco(dev_priv);
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/* Get the CDCLK divide ratio */
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cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
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/*
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* Program the gmbus_freq based on the cdclk frequency.
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* BSpec erroneously claims we should aim for 4MHz, but
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* in fact 1MHz is the correct frequency.
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*/
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if (cdclk_div)
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gmbus_freq = (vco << 1) / cdclk_div;
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if (WARN_ON(gmbus_freq == 0))
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return;
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I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
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}
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void
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intel_i2c_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* In BIOS-less system, program the correct gmbus frequency
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* before reading edid.
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*/
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if (IS_VALLEYVIEW(dev))
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gmbus_set_freq(dev_priv);
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I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
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I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
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}
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static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
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{
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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if (!IS_PINEVIEW(dev_priv->dev))
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return;
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val = I915_READ(DSPCLK_GATE_D);
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if (enable)
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val |= DPCUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, val);
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}
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static u32 get_reserved(struct intel_gmbus *bus)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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struct drm_device *dev = dev_priv->dev;
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u32 reserved = 0;
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/* On most chips, these bits must be preserved in software. */
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if (!IS_I830(dev) && !IS_845G(dev))
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reserved = I915_READ_NOTRACE(bus->gpio_reg) &
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(GPIO_DATA_PULLUP_DISABLE |
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GPIO_CLOCK_PULLUP_DISABLE);
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return reserved;
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}
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static int get_clock(void *data)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
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return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
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}
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static int get_data(void *data)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
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return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
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}
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static void set_clock(void *data, int state_high)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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u32 clock_bits;
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if (state_high)
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clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
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else
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clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
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GPIO_CLOCK_VAL_MASK;
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
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POSTING_READ(bus->gpio_reg);
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}
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static void set_data(void *data, int state_high)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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u32 data_bits;
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if (state_high)
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data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
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else
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data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
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GPIO_DATA_VAL_MASK;
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
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POSTING_READ(bus->gpio_reg);
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}
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static int
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intel_gpio_pre_xfer(struct i2c_adapter *adapter)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_i915_private *dev_priv = bus->dev_priv;
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intel_i2c_reset(dev_priv->dev);
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intel_i2c_quirk_set(dev_priv, true);
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set_data(bus, 1);
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set_clock(bus, 1);
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udelay(I2C_RISEFALL_TIME);
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return 0;
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}
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static void
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intel_gpio_post_xfer(struct i2c_adapter *adapter)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_i915_private *dev_priv = bus->dev_priv;
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set_data(bus, 1);
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set_clock(bus, 1);
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intel_i2c_quirk_set(dev_priv, false);
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}
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static void
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intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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struct i2c_algo_bit_data *algo;
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algo = &bus->bit_algo;
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/* -1 to map pin pair to gmbus index */
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bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
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bus->adapter.algo_data = algo;
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algo->setsda = set_data;
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algo->setscl = set_clock;
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algo->getsda = get_data;
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algo->getscl = get_clock;
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algo->pre_xfer = intel_gpio_pre_xfer;
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algo->post_xfer = intel_gpio_post_xfer;
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algo->udelay = I2C_RISEFALL_TIME;
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algo->timeout = usecs_to_jiffies(2200);
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algo->data = bus;
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}
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/*
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* gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
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* mode. This results in spurious interrupt warnings if the legacy irq no. is
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* shared with another device. The kernel then disables that interrupt source
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* and so prevents the other device from working properly.
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*/
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#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
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static int
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gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
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u32 gmbus2_status,
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u32 gmbus4_irq_en)
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{
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int i;
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int reg_offset = dev_priv->gpio_mmio_base;
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u32 gmbus2 = 0;
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DEFINE_WAIT(wait);
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if (!HAS_GMBUS_IRQ(dev_priv->dev))
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gmbus4_irq_en = 0;
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/* Important: The hw handles only the first bit, so set only one! Since
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* we also need to check for NAKs besides the hw ready/idle signal, we
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* need to wake up periodically and check that ourselves. */
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I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
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for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
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prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
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TASK_UNINTERRUPTIBLE);
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gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
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if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
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break;
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schedule_timeout(1);
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}
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finish_wait(&dev_priv->gmbus_wait_queue, &wait);
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I915_WRITE(GMBUS4 + reg_offset, 0);
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if (gmbus2 & GMBUS_SATOER)
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return -ENXIO;
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if (gmbus2 & gmbus2_status)
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return 0;
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return -ETIMEDOUT;
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}
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static int
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gmbus_wait_idle(struct drm_i915_private *dev_priv)
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{
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int ret;
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int reg_offset = dev_priv->gpio_mmio_base;
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#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
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if (!HAS_GMBUS_IRQ(dev_priv->dev))
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return wait_for(C, 10);
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/* Important: The hw handles only the first bit, so set only one! */
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I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
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ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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msecs_to_jiffies_timeout(10));
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I915_WRITE(GMBUS4 + reg_offset, 0);
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if (ret)
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return 0;
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else
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return -ETIMEDOUT;
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#undef C
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}
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static int
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gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
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u32 gmbus1_index)
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{
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int reg_offset = dev_priv->gpio_mmio_base;
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u16 len = msg->len;
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u8 *buf = msg->buf;
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I915_WRITE(GMBUS1 + reg_offset,
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gmbus1_index |
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GMBUS_CYCLE_WAIT |
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(len << GMBUS_BYTE_COUNT_SHIFT) |
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(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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while (len) {
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int ret;
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u32 val, loop = 0;
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ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
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GMBUS_HW_RDY_EN);
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if (ret)
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return ret;
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val = I915_READ(GMBUS3 + reg_offset);
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do {
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*buf++ = val & 0xff;
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val >>= 8;
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} while (--len && ++loop < 4);
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}
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return 0;
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}
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static int
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gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
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{
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int reg_offset = dev_priv->gpio_mmio_base;
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u16 len = msg->len;
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u8 *buf = msg->buf;
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u32 val, loop;
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val = loop = 0;
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while (len && loop < 4) {
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val |= *buf++ << (8 * loop++);
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len -= 1;
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}
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I915_WRITE(GMBUS3 + reg_offset, val);
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I915_WRITE(GMBUS1 + reg_offset,
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GMBUS_CYCLE_WAIT |
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(msg->len << GMBUS_BYTE_COUNT_SHIFT) |
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(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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while (len) {
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int ret;
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val = loop = 0;
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do {
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val |= *buf++ << (8 * loop);
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} while (--len && ++loop < 4);
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I915_WRITE(GMBUS3 + reg_offset, val);
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ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
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GMBUS_HW_RDY_EN);
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if (ret)
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return ret;
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}
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return 0;
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}
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/*
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* The gmbus controller can combine a 1 or 2 byte write with a read that
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* immediately follows it by using an "INDEX" cycle.
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*/
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static bool
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gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
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{
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return (i + 1 < num &&
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!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
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(msgs[i + 1].flags & I2C_M_RD));
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}
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static int
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gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
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{
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int reg_offset = dev_priv->gpio_mmio_base;
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u32 gmbus1_index = 0;
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u32 gmbus5 = 0;
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int ret;
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if (msgs[0].len == 2)
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gmbus5 = GMBUS_2BYTE_INDEX_EN |
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msgs[0].buf[1] | (msgs[0].buf[0] << 8);
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if (msgs[0].len == 1)
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gmbus1_index = GMBUS_CYCLE_INDEX |
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(msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
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/* GMBUS5 holds 16-bit index */
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if (gmbus5)
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I915_WRITE(GMBUS5 + reg_offset, gmbus5);
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ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
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/* Clear GMBUS5 after each index transfer */
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if (gmbus5)
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I915_WRITE(GMBUS5 + reg_offset, 0);
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return ret;
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}
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static int
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gmbus_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs,
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int num)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_i915_private *dev_priv = bus->dev_priv;
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int i, reg_offset;
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int ret = 0;
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intel_aux_display_runtime_get(dev_priv);
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mutex_lock(&dev_priv->gmbus_mutex);
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if (bus->force_bit) {
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ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
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goto out;
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}
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reg_offset = dev_priv->gpio_mmio_base;
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I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
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for (i = 0; i < num; i++) {
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if (gmbus_is_index_read(msgs, i, num)) {
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ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
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i += 1; /* set i to the index of the read xfer */
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} else if (msgs[i].flags & I2C_M_RD) {
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ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
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} else {
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ret = gmbus_xfer_write(dev_priv, &msgs[i]);
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}
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if (ret == -ETIMEDOUT)
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goto timeout;
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if (ret == -ENXIO)
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goto clear_err;
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ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
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GMBUS_HW_WAIT_EN);
|
|
if (ret == -ENXIO)
|
|
goto clear_err;
|
|
if (ret)
|
|
goto timeout;
|
|
}
|
|
|
|
/* Generate a STOP condition on the bus. Note that gmbus can't generata
|
|
* a STOP on the very first cycle. To simplify the code we
|
|
* unconditionally generate the STOP condition with an additional gmbus
|
|
* cycle. */
|
|
I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
|
|
|
|
/* Mark the GMBUS interface as disabled after waiting for idle.
|
|
* We will re-enable it at the start of the next xfer,
|
|
* till then let it sleep.
|
|
*/
|
|
if (gmbus_wait_idle(dev_priv)) {
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
|
|
adapter->name);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
I915_WRITE(GMBUS0 + reg_offset, 0);
|
|
ret = ret ?: i;
|
|
goto out;
|
|
|
|
clear_err:
|
|
/*
|
|
* Wait for bus to IDLE before clearing NAK.
|
|
* If we clear the NAK while bus is still active, then it will stay
|
|
* active and the next transaction may fail.
|
|
*
|
|
* If no ACK is received during the address phase of a transaction, the
|
|
* adapter must report -ENXIO. It is not clear what to return if no ACK
|
|
* is received at other times. But we have to be careful to not return
|
|
* spurious -ENXIO because that will prevent i2c and drm edid functions
|
|
* from retrying. So return -ENXIO only when gmbus properly quiescents -
|
|
* timing out seems to happen when there _is_ a ddc chip present, but
|
|
* it's slow responding and only answers on the 2nd retry.
|
|
*/
|
|
ret = -ENXIO;
|
|
if (gmbus_wait_idle(dev_priv)) {
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
|
|
adapter->name);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
|
|
/* Toggle the Software Clear Interrupt bit. This has the effect
|
|
* of resetting the GMBUS controller and so clearing the
|
|
* BUS_ERROR raised by the slave's NAK.
|
|
*/
|
|
I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
|
|
I915_WRITE(GMBUS1 + reg_offset, 0);
|
|
I915_WRITE(GMBUS0 + reg_offset, 0);
|
|
|
|
DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
|
|
adapter->name, msgs[i].addr,
|
|
(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
|
|
|
|
goto out;
|
|
|
|
timeout:
|
|
DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
|
|
bus->adapter.name, bus->reg0 & 0xff);
|
|
I915_WRITE(GMBUS0 + reg_offset, 0);
|
|
|
|
/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
|
|
bus->force_bit = 1;
|
|
ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
|
|
|
|
out:
|
|
mutex_unlock(&dev_priv->gmbus_mutex);
|
|
intel_aux_display_runtime_put(dev_priv);
|
|
return ret;
|
|
}
|
|
|
|
static u32 gmbus_func(struct i2c_adapter *adapter)
|
|
{
|
|
return i2c_bit_algo.functionality(adapter) &
|
|
(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
|
|
/* I2C_FUNC_10BIT_ADDR | */
|
|
I2C_FUNC_SMBUS_READ_BLOCK_DATA |
|
|
I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
|
|
}
|
|
|
|
static const struct i2c_algorithm gmbus_algorithm = {
|
|
.master_xfer = gmbus_xfer,
|
|
.functionality = gmbus_func
|
|
};
|
|
|
|
/**
|
|
* intel_gmbus_setup - instantiate all Intel i2c GMBuses
|
|
* @dev: DRM device
|
|
*/
|
|
int intel_setup_gmbus(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int ret, i;
|
|
|
|
if (HAS_PCH_NOP(dev))
|
|
return 0;
|
|
else if (HAS_PCH_SPLIT(dev))
|
|
dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
|
|
else if (IS_VALLEYVIEW(dev))
|
|
dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
|
|
else
|
|
dev_priv->gpio_mmio_base = 0;
|
|
|
|
mutex_init(&dev_priv->gmbus_mutex);
|
|
init_waitqueue_head(&dev_priv->gmbus_wait_queue);
|
|
|
|
for (i = 0; i < GMBUS_NUM_PORTS; i++) {
|
|
struct intel_gmbus *bus = &dev_priv->gmbus[i];
|
|
u32 port = i + 1; /* +1 to map gmbus index to pin pair */
|
|
|
|
bus->adapter.owner = THIS_MODULE;
|
|
bus->adapter.class = I2C_CLASS_DDC;
|
|
snprintf(bus->adapter.name,
|
|
sizeof(bus->adapter.name),
|
|
"i915 gmbus %s",
|
|
gmbus_ports[i].name);
|
|
|
|
bus->adapter.dev.parent = &dev->pdev->dev;
|
|
bus->dev_priv = dev_priv;
|
|
|
|
bus->adapter.algo = &gmbus_algorithm;
|
|
|
|
/* By default use a conservative clock rate */
|
|
bus->reg0 = port | GMBUS_RATE_100KHZ;
|
|
|
|
/* gmbus seems to be broken on i830 */
|
|
if (IS_I830(dev))
|
|
bus->force_bit = 1;
|
|
|
|
intel_gpio_setup(bus, port);
|
|
|
|
ret = i2c_add_adapter(&bus->adapter);
|
|
if (ret)
|
|
goto err;
|
|
}
|
|
|
|
intel_i2c_reset(dev_priv->dev);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
while (--i) {
|
|
struct intel_gmbus *bus = &dev_priv->gmbus[i];
|
|
i2c_del_adapter(&bus->adapter);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
|
|
unsigned port)
|
|
{
|
|
WARN_ON(!intel_gmbus_is_port_valid(port));
|
|
/* -1 to map pin pair to gmbus index */
|
|
return (intel_gmbus_is_port_valid(port)) ?
|
|
&dev_priv->gmbus[port - 1].adapter : NULL;
|
|
}
|
|
|
|
void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
|
|
{
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
|
|
bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
|
|
}
|
|
|
|
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
|
|
{
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
|
|
bus->force_bit += force_bit ? 1 : -1;
|
|
DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
|
|
force_bit ? "en" : "dis", adapter->name,
|
|
bus->force_bit);
|
|
}
|
|
|
|
void intel_teardown_gmbus(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int i;
|
|
|
|
for (i = 0; i < GMBUS_NUM_PORTS; i++) {
|
|
struct intel_gmbus *bus = &dev_priv->gmbus[i];
|
|
i2c_del_adapter(&bus->adapter);
|
|
}
|
|
}
|