dcf1cece14
This adds DSA switch instantiation hooks to the orion5x and the kirkwood ARM SoC platform code, and instantiates the DSA switch driver on the 88F5181L FXO RD, the 88F5181L GE RD, the 6183 AP GE RD, the Linksys WRT350n v2, and the 88F6281 RD boards. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Nicolas Pitre <nico@marvell.com> Tested-by: Peter van Valderen <linux@ddcrew.com> Tested-by: Dirk Teurlings <dirk@upexia.nl> Signed-off-by: Nicolas Pitre <nico@marvell.com>
176 lines
4.9 KiB
C
176 lines
4.9 KiB
C
/*
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* arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
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*
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* Marvell Orion-VoIP FXO Reference Design Setup
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ethtool.h>
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#include <net/dsa.h>
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#include <asm/mach-types.h>
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#include <asm/gpio.h>
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#include <asm/leds.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include <mach/orion5x.h>
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#include "common.h"
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#include "mpp.h"
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/*****************************************************************************
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* RD-88F5181L FXO Info
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****************************************************************************/
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/*
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* 8M NOR flash Device bus boot chip select
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*/
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#define RD88F5181L_FXO_NOR_BOOT_BASE 0xff800000
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#define RD88F5181L_FXO_NOR_BOOT_SIZE SZ_8M
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/*****************************************************************************
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* 8M NOR Flash on Device bus Boot chip select
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****************************************************************************/
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static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = {
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.width = 1,
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};
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static struct resource rd88f5181l_fxo_nor_boot_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = RD88F5181L_FXO_NOR_BOOT_BASE,
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.end = RD88F5181L_FXO_NOR_BOOT_BASE +
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RD88F5181L_FXO_NOR_BOOT_SIZE - 1,
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};
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static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &rd88f5181l_fxo_nor_boot_flash_data,
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},
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.num_resources = 1,
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.resource = &rd88f5181l_fxo_nor_boot_flash_resource,
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};
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/*****************************************************************************
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* General Setup
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****************************************************************************/
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static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
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{ 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */
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{ 1, MPP_GPIO }, /* PCI_intA */
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{ 2, MPP_GPIO }, /* Hard Reset / Factory Init*/
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{ 3, MPP_GPIO }, /* FXS or DAA select */
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{ 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */
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{ 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */
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{ 6, MPP_PCI_CLK }, /* CPU PCI refclk */
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{ 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
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{ 8, MPP_GPIO }, /* CardBus reset */
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{ 9, MPP_GPIO }, /* GE_RXERR */
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{ 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */
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{ 11, MPP_GPIO }, /* Lifeline control */
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{ 12, MPP_GIGE }, /* GE_TXD[4] */
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{ 13, MPP_GIGE }, /* GE_TXD[5] */
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{ 14, MPP_GIGE }, /* GE_TXD[6] */
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{ 15, MPP_GIGE }, /* GE_TXD[7] */
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{ 16, MPP_GIGE }, /* GE_RXD[4] */
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{ 17, MPP_GIGE }, /* GE_RXD[5] */
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{ 18, MPP_GIGE }, /* GE_RXD[6] */
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{ 19, MPP_GIGE }, /* GE_RXD[7] */
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{ -1 },
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};
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static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
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.phy_addr = MV643XX_ETH_PHY_NONE,
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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};
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static struct dsa_platform_data rd88f5181l_fxo_switch_data = {
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.port_names[0] = "lan2",
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.port_names[1] = "lan1",
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.port_names[2] = "wan",
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.port_names[3] = "cpu",
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.port_names[5] = "lan4",
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.port_names[7] = "lan3",
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};
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static void __init rd88f5181l_fxo_init(void)
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{
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes);
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/*
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* Configure peripherals.
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*/
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orion5x_ehci0_init();
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orion5x_eth_init(&rd88f5181l_fxo_eth_data);
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orion5x_eth_switch_init(&rd88f5181l_fxo_switch_data, NO_IRQ);
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orion5x_uart0_init();
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orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE,
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RD88F5181L_FXO_NOR_BOOT_SIZE);
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platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
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}
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static int __init
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rd88f5181l_fxo_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* Mini-PCI / Cardbus slot.
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*/
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return gpio_to_irq(1);
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}
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static struct hw_pci rd88f5181l_fxo_pci __initdata = {
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.nr_controllers = 2,
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.swizzle = pci_std_swizzle,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = rd88f5181l_fxo_pci_map_irq,
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};
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static int __init rd88f5181l_fxo_pci_init(void)
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{
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if (machine_is_rd88f5181l_fxo()) {
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orion5x_pci_set_cardbus_mode();
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pci_common_init(&rd88f5181l_fxo_pci);
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}
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return 0;
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}
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subsys_initcall(rd88f5181l_fxo_pci_init);
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MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
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/* Maintainer: Nicolas Pitre <nico@marvell.com> */
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.phys_io = ORION5X_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = rd88f5181l_fxo_init,
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.map_io = orion5x_map_io,
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.init_irq = orion5x_init_irq,
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.timer = &orion5x_timer,
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.fixup = tag_fixup_mem32,
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MACHINE_END
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