![Thierry Reding](/assets/img/avatar_default.png)
Parameterize more parts of the driver and add support for Tegra210. Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
1332 lines
33 KiB
C
1332 lines
33 KiB
C
/*
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* NVIDIA Tegra xHCI host controller driver
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*
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* Copyright (C) 2014 NVIDIA Corporation
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* Copyright (C) 2014 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/phy/tegra/xusb.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include "xhci.h"
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#define TEGRA_XHCI_SS_HIGH_SPEED 120000000
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#define TEGRA_XHCI_SS_LOW_SPEED 12000000
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/* FPCI CFG registers */
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#define XUSB_CFG_1 0x004
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#define XUSB_IO_SPACE_EN BIT(0)
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#define XUSB_MEM_SPACE_EN BIT(1)
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#define XUSB_BUS_MASTER_EN BIT(2)
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#define XUSB_CFG_4 0x010
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#define XUSB_BASE_ADDR_SHIFT 15
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#define XUSB_BASE_ADDR_MASK 0x1ffff
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#define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
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#define XUSB_CFG_CSB_BASE_ADDR 0x800
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/* FPCI mailbox registers */
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#define XUSB_CFG_ARU_MBOX_CMD 0x0e4
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#define MBOX_DEST_FALC BIT(27)
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#define MBOX_DEST_PME BIT(28)
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#define MBOX_DEST_SMI BIT(29)
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#define MBOX_DEST_XHCI BIT(30)
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#define MBOX_INT_EN BIT(31)
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#define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8
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#define CMD_DATA_SHIFT 0
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#define CMD_DATA_MASK 0xffffff
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#define CMD_TYPE_SHIFT 24
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#define CMD_TYPE_MASK 0xff
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#define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec
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#define XUSB_CFG_ARU_MBOX_OWNER 0x0f0
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#define MBOX_OWNER_NONE 0
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#define MBOX_OWNER_FW 1
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#define MBOX_OWNER_SW 2
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#define XUSB_CFG_ARU_SMI_INTR 0x428
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#define MBOX_SMI_INTR_FW_HANG BIT(1)
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#define MBOX_SMI_INTR_EN BIT(3)
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/* IPFS registers */
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#define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
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#define IPFS_EN_FPCI BIT(0)
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#define IPFS_XUSB_HOST_INTR_MASK_0 0x188
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#define IPFS_IP_INT_MASK BIT(16)
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#define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
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#define CSB_PAGE_SELECT_MASK 0x7fffff
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#define CSB_PAGE_SELECT_SHIFT 9
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#define CSB_PAGE_OFFSET_MASK 0x1ff
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#define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
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CSB_PAGE_SELECT_MASK)
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#define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
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/* Falcon CSB registers */
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#define XUSB_FALC_CPUCTL 0x100
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#define CPUCTL_STARTCPU BIT(1)
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#define CPUCTL_STATE_HALTED BIT(4)
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#define CPUCTL_STATE_STOPPED BIT(5)
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#define XUSB_FALC_BOOTVEC 0x104
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#define XUSB_FALC_DMACTL 0x10c
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#define XUSB_FALC_IMFILLRNG1 0x154
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#define IMFILLRNG1_TAG_MASK 0xffff
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#define IMFILLRNG1_TAG_LO_SHIFT 0
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#define IMFILLRNG1_TAG_HI_SHIFT 16
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#define XUSB_FALC_IMFILLCTL 0x158
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/* MP CSB registers */
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#define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
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#define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
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#define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
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#define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
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#define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
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#define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
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#define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
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#define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
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#define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
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#define L2IMEMOP_ACTION_SHIFT 24
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#define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
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#define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
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#define XUSB_CSB_MP_APMAP 0x10181c
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#define APMAP_BOOTPATH BIT(31)
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#define IMEM_BLOCK_SIZE 256
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struct tegra_xusb_fw_header {
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u32 boot_loadaddr_in_imem;
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u32 boot_codedfi_offset;
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u32 boot_codetag;
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u32 boot_codesize;
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u32 phys_memaddr;
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u16 reqphys_memsize;
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u16 alloc_phys_memsize;
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u32 rodata_img_offset;
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u32 rodata_section_start;
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u32 rodata_section_end;
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u32 main_fnaddr;
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u32 fwimg_cksum;
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u32 fwimg_created_time;
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u32 imem_resident_start;
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u32 imem_resident_end;
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u32 idirect_start;
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u32 idirect_end;
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u32 l2_imem_start;
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u32 l2_imem_end;
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u32 version_id;
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u8 init_ddirect;
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u8 reserved[3];
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u32 phys_addr_log_buffer;
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u32 total_log_entries;
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u32 dequeue_ptr;
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u32 dummy_var[2];
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u32 fwimg_len;
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u8 magic[8];
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u32 ss_low_power_entry_timeout;
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u8 num_hsic_port;
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u8 padding[139]; /* Pad to 256 bytes */
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};
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struct tegra_xusb_phy_type {
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const char *name;
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unsigned int num;
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};
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struct tegra_xusb_soc {
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const char *firmware;
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const char * const *supply_names;
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unsigned int num_supplies;
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const struct tegra_xusb_phy_type *phy_types;
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unsigned int num_types;
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struct {
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struct {
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unsigned int offset;
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unsigned int count;
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} usb2, ulpi, hsic, usb3;
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} ports;
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bool scale_ss_clock;
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};
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struct tegra_xusb {
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struct device *dev;
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void __iomem *regs;
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struct usb_hcd *hcd;
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struct mutex lock;
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int xhci_irq;
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int mbox_irq;
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void __iomem *ipfs_base;
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void __iomem *fpci_base;
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const struct tegra_xusb_soc *soc;
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struct regulator_bulk_data *supplies;
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struct tegra_xusb_padctl *padctl;
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struct clk *host_clk;
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struct clk *falcon_clk;
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struct clk *ss_clk;
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struct clk *ss_src_clk;
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struct clk *hs_src_clk;
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struct clk *fs_src_clk;
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struct clk *pll_u_480m;
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struct clk *clk_m;
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struct clk *pll_e;
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struct reset_control *host_rst;
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struct reset_control *ss_rst;
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struct phy **phys;
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unsigned int num_phys;
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/* Firmware loading related */
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struct {
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size_t size;
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void *virt;
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dma_addr_t phys;
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} fw;
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};
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static struct hc_driver __read_mostly tegra_xhci_hc_driver;
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static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
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{
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return readl(tegra->fpci_base + offset);
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}
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static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
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unsigned int offset)
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{
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writel(value, tegra->fpci_base + offset);
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}
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static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
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{
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return readl(tegra->ipfs_base + offset);
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}
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static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
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unsigned int offset)
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{
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writel(value, tegra->ipfs_base + offset);
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}
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static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
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{
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u32 page = CSB_PAGE_SELECT(offset);
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u32 ofs = CSB_PAGE_OFFSET(offset);
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fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
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return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
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}
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static void csb_writel(struct tegra_xusb *tegra, u32 value,
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unsigned int offset)
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{
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u32 page = CSB_PAGE_SELECT(offset);
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u32 ofs = CSB_PAGE_OFFSET(offset);
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fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
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fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
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}
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static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
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unsigned long rate)
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{
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unsigned long new_parent_rate, old_parent_rate;
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struct clk *clk = tegra->ss_src_clk;
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unsigned int div;
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int err;
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if (clk_get_rate(clk) == rate)
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return 0;
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switch (rate) {
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case TEGRA_XHCI_SS_HIGH_SPEED:
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/*
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* Reparent to PLLU_480M. Set divider first to avoid
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* overclocking.
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*/
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old_parent_rate = clk_get_rate(clk_get_parent(clk));
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new_parent_rate = clk_get_rate(tegra->pll_u_480m);
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div = new_parent_rate / rate;
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err = clk_set_rate(clk, old_parent_rate / div);
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if (err)
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return err;
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err = clk_set_parent(clk, tegra->pll_u_480m);
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if (err)
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return err;
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/*
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* The rate should already be correct, but set it again just
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* to be sure.
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*/
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err = clk_set_rate(clk, rate);
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if (err)
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return err;
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break;
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case TEGRA_XHCI_SS_LOW_SPEED:
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/* Reparent to CLK_M */
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err = clk_set_parent(clk, tegra->clk_m);
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if (err)
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return err;
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err = clk_set_rate(clk, rate);
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if (err)
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return err;
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break;
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default:
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dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
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return -EINVAL;
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}
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if (clk_get_rate(clk) != rate) {
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dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
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return -EINVAL;
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}
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return 0;
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}
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static unsigned long extract_field(u32 value, unsigned int start,
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unsigned int count)
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{
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return (value >> start) & ((1 << count) - 1);
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}
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/* Command requests from the firmware */
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enum tegra_xusb_mbox_cmd {
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MBOX_CMD_MSG_ENABLED = 1,
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MBOX_CMD_INC_FALC_CLOCK,
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MBOX_CMD_DEC_FALC_CLOCK,
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MBOX_CMD_INC_SSPI_CLOCK,
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MBOX_CMD_DEC_SSPI_CLOCK,
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MBOX_CMD_SET_BW, /* no ACK/NAK required */
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MBOX_CMD_SET_SS_PWR_GATING,
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MBOX_CMD_SET_SS_PWR_UNGATING,
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MBOX_CMD_SAVE_DFE_CTLE_CTX,
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MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
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MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
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MBOX_CMD_START_HSIC_IDLE,
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MBOX_CMD_STOP_HSIC_IDLE,
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MBOX_CMD_DBC_WAKE_STACK, /* unused */
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MBOX_CMD_HSIC_PRETEND_CONNECT,
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MBOX_CMD_RESET_SSPI,
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MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
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MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
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MBOX_CMD_MAX,
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/* Response message to above commands */
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MBOX_CMD_ACK = 128,
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MBOX_CMD_NAK
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};
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static const char * const mbox_cmd_name[] = {
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[ 1] = "MSG_ENABLE",
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[ 2] = "INC_FALCON_CLOCK",
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[ 3] = "DEC_FALCON_CLOCK",
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[ 4] = "INC_SSPI_CLOCK",
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[ 5] = "DEC_SSPI_CLOCK",
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[ 6] = "SET_BW",
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[ 7] = "SET_SS_PWR_GATING",
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[ 8] = "SET_SS_PWR_UNGATING",
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[ 9] = "SAVE_DFE_CTLE_CTX",
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[ 10] = "AIRPLANE_MODE_ENABLED",
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[ 11] = "AIRPLANE_MODE_DISABLED",
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[ 12] = "START_HSIC_IDLE",
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[ 13] = "STOP_HSIC_IDLE",
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[ 14] = "DBC_WAKE_STACK",
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[ 15] = "HSIC_PRETEND_CONNECT",
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[ 16] = "RESET_SSPI",
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[ 17] = "DISABLE_SS_LFPS_DETECTION",
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[ 18] = "ENABLE_SS_LFPS_DETECTION",
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[128] = "ACK",
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[129] = "NAK",
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};
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struct tegra_xusb_mbox_msg {
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u32 cmd;
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u32 data;
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};
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static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
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{
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return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
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(msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
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}
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static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
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u32 value)
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{
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msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
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msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
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}
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static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
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{
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switch (cmd) {
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case MBOX_CMD_SET_BW:
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case MBOX_CMD_ACK:
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case MBOX_CMD_NAK:
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return false;
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default:
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return true;
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}
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}
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static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
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const struct tegra_xusb_mbox_msg *msg)
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{
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bool wait_for_idle = false;
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u32 value;
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/*
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* Acquire the mailbox. The firmware still owns the mailbox for
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* ACK/NAK messages.
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*/
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if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
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value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
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if (value != MBOX_OWNER_NONE) {
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dev_err(tegra->dev, "mailbox is busy\n");
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return -EBUSY;
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}
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fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
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value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
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if (value != MBOX_OWNER_SW) {
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dev_err(tegra->dev, "failed to acquire mailbox\n");
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return -EBUSY;
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}
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wait_for_idle = true;
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}
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value = tegra_xusb_mbox_pack(msg);
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fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
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value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
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value |= MBOX_INT_EN | MBOX_DEST_FALC;
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fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
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if (wait_for_idle) {
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unsigned long timeout = jiffies + msecs_to_jiffies(250);
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while (time_before(jiffies, timeout)) {
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value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
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if (value == MBOX_OWNER_NONE)
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break;
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usleep_range(10, 20);
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}
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if (time_after(jiffies, timeout))
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value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
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if (value != MBOX_OWNER_NONE)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
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{
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struct tegra_xusb *tegra = data;
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u32 value;
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/* clear mailbox interrupts */
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value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
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fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
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if (value & MBOX_SMI_INTR_FW_HANG)
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dev_err(tegra->dev, "controller firmware hang\n");
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return IRQ_WAKE_THREAD;
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}
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static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
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const struct tegra_xusb_mbox_msg *msg)
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{
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struct tegra_xusb_padctl *padctl = tegra->padctl;
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const struct tegra_xusb_soc *soc = tegra->soc;
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struct device *dev = tegra->dev;
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struct tegra_xusb_mbox_msg rsp;
|
|
unsigned long mask;
|
|
unsigned int port;
|
|
bool idle, enable;
|
|
int err;
|
|
|
|
memset(&rsp, 0, sizeof(rsp));
|
|
|
|
switch (msg->cmd) {
|
|
case MBOX_CMD_INC_FALC_CLOCK:
|
|
case MBOX_CMD_DEC_FALC_CLOCK:
|
|
rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
|
|
if (rsp.data != msg->data)
|
|
rsp.cmd = MBOX_CMD_NAK;
|
|
else
|
|
rsp.cmd = MBOX_CMD_ACK;
|
|
|
|
break;
|
|
|
|
case MBOX_CMD_INC_SSPI_CLOCK:
|
|
case MBOX_CMD_DEC_SSPI_CLOCK:
|
|
if (tegra->soc->scale_ss_clock) {
|
|
err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
|
|
if (err < 0)
|
|
rsp.cmd = MBOX_CMD_NAK;
|
|
else
|
|
rsp.cmd = MBOX_CMD_ACK;
|
|
|
|
rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
|
|
} else {
|
|
rsp.cmd = MBOX_CMD_ACK;
|
|
rsp.data = msg->data;
|
|
}
|
|
|
|
break;
|
|
|
|
case MBOX_CMD_SET_BW:
|
|
/*
|
|
* TODO: Request bandwidth once EMC scaling is supported.
|
|
* Ignore for now since ACK/NAK is not required for SET_BW
|
|
* messages.
|
|
*/
|
|
break;
|
|
|
|
case MBOX_CMD_SAVE_DFE_CTLE_CTX:
|
|
err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to save context for USB3#%u: %d\n",
|
|
msg->data, err);
|
|
rsp.cmd = MBOX_CMD_NAK;
|
|
} else {
|
|
rsp.cmd = MBOX_CMD_ACK;
|
|
}
|
|
|
|
rsp.data = msg->data;
|
|
break;
|
|
|
|
case MBOX_CMD_START_HSIC_IDLE:
|
|
case MBOX_CMD_STOP_HSIC_IDLE:
|
|
if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
|
|
idle = false;
|
|
else
|
|
idle = true;
|
|
|
|
mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
|
|
soc->ports.hsic.count);
|
|
|
|
for_each_set_bit(port, &mask, 32) {
|
|
err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
|
|
idle);
|
|
if (err < 0)
|
|
break;
|
|
}
|
|
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
|
|
idle ? "idle" : "busy", err);
|
|
rsp.cmd = MBOX_CMD_NAK;
|
|
} else {
|
|
rsp.cmd = MBOX_CMD_ACK;
|
|
}
|
|
|
|
rsp.data = msg->data;
|
|
break;
|
|
|
|
case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
|
|
case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
|
|
if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
|
|
enable = false;
|
|
else
|
|
enable = true;
|
|
|
|
mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
|
|
soc->ports.usb3.count);
|
|
|
|
for_each_set_bit(port, &mask, soc->ports.usb3.count) {
|
|
err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
|
|
port,
|
|
enable);
|
|
if (err < 0)
|
|
break;
|
|
}
|
|
|
|
if (err < 0) {
|
|
dev_err(dev,
|
|
"failed to %s LFPS detection on USB3#%u: %d\n",
|
|
enable ? "enable" : "disable", port, err);
|
|
rsp.cmd = MBOX_CMD_NAK;
|
|
} else {
|
|
rsp.cmd = MBOX_CMD_ACK;
|
|
}
|
|
|
|
rsp.data = msg->data;
|
|
break;
|
|
|
|
default:
|
|
dev_warn(dev, "unknown message: %#x\n", msg->cmd);
|
|
break;
|
|
}
|
|
|
|
if (rsp.cmd) {
|
|
const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
|
|
|
|
err = tegra_xusb_mbox_send(tegra, &rsp);
|
|
if (err < 0)
|
|
dev_err(dev, "failed to send %s: %d\n", cmd, err);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
|
|
{
|
|
struct tegra_xusb *tegra = data;
|
|
struct tegra_xusb_mbox_msg msg;
|
|
u32 value;
|
|
|
|
mutex_lock(&tegra->lock);
|
|
|
|
value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
|
|
tegra_xusb_mbox_unpack(&msg, value);
|
|
|
|
value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
|
|
value &= ~MBOX_DEST_SMI;
|
|
fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
|
|
|
|
/* clear mailbox owner if no ACK/NAK is required */
|
|
if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
|
|
fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
|
|
|
|
tegra_xusb_mbox_handle(tegra, &msg);
|
|
|
|
mutex_unlock(&tegra->lock);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra,
|
|
struct resource *regs)
|
|
{
|
|
u32 value;
|
|
|
|
value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
|
|
value |= IPFS_EN_FPCI;
|
|
ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
|
|
|
|
usleep_range(10, 20);
|
|
|
|
/* Program BAR0 space */
|
|
value = fpci_readl(tegra, XUSB_CFG_4);
|
|
value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
|
|
value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
|
|
fpci_writel(tegra, value, XUSB_CFG_4);
|
|
|
|
usleep_range(100, 200);
|
|
|
|
/* Enable bus master */
|
|
value = fpci_readl(tegra, XUSB_CFG_1);
|
|
value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
|
|
fpci_writel(tegra, value, XUSB_CFG_1);
|
|
|
|
/* Enable interrupt assertion */
|
|
value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
|
|
value |= IPFS_IP_INT_MASK;
|
|
ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
|
|
|
|
/* Set hysteresis */
|
|
ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
|
|
}
|
|
|
|
static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
|
|
{
|
|
int err;
|
|
|
|
err = clk_prepare_enable(tegra->pll_e);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = clk_prepare_enable(tegra->host_clk);
|
|
if (err < 0)
|
|
goto disable_plle;
|
|
|
|
err = clk_prepare_enable(tegra->ss_clk);
|
|
if (err < 0)
|
|
goto disable_host;
|
|
|
|
err = clk_prepare_enable(tegra->falcon_clk);
|
|
if (err < 0)
|
|
goto disable_ss;
|
|
|
|
err = clk_prepare_enable(tegra->fs_src_clk);
|
|
if (err < 0)
|
|
goto disable_falc;
|
|
|
|
err = clk_prepare_enable(tegra->hs_src_clk);
|
|
if (err < 0)
|
|
goto disable_fs_src;
|
|
|
|
if (tegra->soc->scale_ss_clock) {
|
|
err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
|
|
if (err < 0)
|
|
goto disable_hs_src;
|
|
}
|
|
|
|
return 0;
|
|
|
|
disable_hs_src:
|
|
clk_disable_unprepare(tegra->hs_src_clk);
|
|
disable_fs_src:
|
|
clk_disable_unprepare(tegra->fs_src_clk);
|
|
disable_falc:
|
|
clk_disable_unprepare(tegra->falcon_clk);
|
|
disable_ss:
|
|
clk_disable_unprepare(tegra->ss_clk);
|
|
disable_host:
|
|
clk_disable_unprepare(tegra->host_clk);
|
|
disable_plle:
|
|
clk_disable_unprepare(tegra->pll_e);
|
|
return err;
|
|
}
|
|
|
|
static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
|
|
{
|
|
clk_disable_unprepare(tegra->pll_e);
|
|
clk_disable_unprepare(tegra->host_clk);
|
|
clk_disable_unprepare(tegra->ss_clk);
|
|
clk_disable_unprepare(tegra->falcon_clk);
|
|
clk_disable_unprepare(tegra->fs_src_clk);
|
|
clk_disable_unprepare(tegra->hs_src_clk);
|
|
}
|
|
|
|
static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
|
|
{
|
|
unsigned int i;
|
|
int err;
|
|
|
|
for (i = 0; i < tegra->num_phys; i++) {
|
|
err = phy_init(tegra->phys[i]);
|
|
if (err)
|
|
goto disable_phy;
|
|
|
|
err = phy_power_on(tegra->phys[i]);
|
|
if (err) {
|
|
phy_exit(tegra->phys[i]);
|
|
goto disable_phy;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
disable_phy:
|
|
while (i--) {
|
|
phy_power_off(tegra->phys[i]);
|
|
phy_exit(tegra->phys[i]);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < tegra->num_phys; i++) {
|
|
phy_power_off(tegra->phys[i]);
|
|
phy_exit(tegra->phys[i]);
|
|
}
|
|
}
|
|
|
|
static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
|
|
{
|
|
unsigned int code_tag_blocks, code_size_blocks, code_blocks;
|
|
struct tegra_xusb_fw_header *header;
|
|
struct device *dev = tegra->dev;
|
|
const struct firmware *fw;
|
|
unsigned long timeout;
|
|
time_t timestamp;
|
|
struct tm time;
|
|
u64 address;
|
|
u32 value;
|
|
int err;
|
|
|
|
err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
|
|
if (err < 0) {
|
|
dev_err(tegra->dev, "failed to request firmware: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
/* Load Falcon controller with its firmware. */
|
|
header = (struct tegra_xusb_fw_header *)fw->data;
|
|
tegra->fw.size = le32_to_cpu(header->fwimg_len);
|
|
|
|
tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
|
|
&tegra->fw.phys, GFP_KERNEL);
|
|
if (!tegra->fw.virt) {
|
|
dev_err(tegra->dev, "failed to allocate memory for firmware\n");
|
|
release_firmware(fw);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
|
|
memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
|
|
release_firmware(fw);
|
|
|
|
if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
|
|
dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
|
|
csb_readl(tegra, XUSB_FALC_CPUCTL));
|
|
return 0;
|
|
}
|
|
|
|
/* Program the size of DFI into ILOAD_ATTR. */
|
|
csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
|
|
|
|
/*
|
|
* Boot code of the firmware reads the ILOAD_BASE registers
|
|
* to get to the start of the DFI in system memory.
|
|
*/
|
|
address = tegra->fw.phys + sizeof(*header);
|
|
csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
|
|
csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
|
|
|
|
/* Set BOOTPATH to 1 in APMAP. */
|
|
csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
|
|
|
|
/* Invalidate L2IMEM. */
|
|
csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
|
|
|
|
/*
|
|
* Initiate fetch of bootcode from system memory into L2IMEM.
|
|
* Program bootcode location and size in system memory.
|
|
*/
|
|
code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
|
|
IMEM_BLOCK_SIZE);
|
|
code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
|
|
IMEM_BLOCK_SIZE);
|
|
code_blocks = code_tag_blocks + code_size_blocks;
|
|
|
|
value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
|
|
L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
|
|
((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
|
|
L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
|
|
csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
|
|
|
|
/* Trigger L2IMEM load operation. */
|
|
csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
|
|
XUSB_CSB_MP_L2IMEMOP_TRIG);
|
|
|
|
/* Setup Falcon auto-fill. */
|
|
csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
|
|
|
|
value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
|
|
IMFILLRNG1_TAG_LO_SHIFT) |
|
|
((code_blocks & IMFILLRNG1_TAG_MASK) <<
|
|
IMFILLRNG1_TAG_HI_SHIFT);
|
|
csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
|
|
|
|
csb_writel(tegra, 0, XUSB_FALC_DMACTL);
|
|
|
|
msleep(50);
|
|
|
|
csb_writel(tegra, le32_to_cpu(header->boot_codetag),
|
|
XUSB_FALC_BOOTVEC);
|
|
|
|
/* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
|
|
timeout = jiffies + msecs_to_jiffies(5);
|
|
|
|
csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
|
|
break;
|
|
|
|
usleep_range(100, 200);
|
|
}
|
|
|
|
if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
|
|
dev_err(dev, "Falcon failed to start, state: %#x\n",
|
|
csb_readl(tegra, XUSB_FALC_CPUCTL));
|
|
return -EIO;
|
|
}
|
|
|
|
timestamp = le32_to_cpu(header->fwimg_created_time);
|
|
time_to_tm(timestamp, 0, &time);
|
|
|
|
dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
|
|
time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
|
|
time.tm_hour, time.tm_min, time.tm_sec);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_xusb_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra_xusb_mbox_msg msg;
|
|
struct resource *res, *regs;
|
|
struct tegra_xusb *tegra;
|
|
struct xhci_hcd *xhci;
|
|
unsigned int i, j, k;
|
|
struct phy *phy;
|
|
int err;
|
|
|
|
BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
|
|
|
|
tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
|
|
if (!tegra)
|
|
return -ENOMEM;
|
|
|
|
tegra->soc = of_device_get_match_data(&pdev->dev);
|
|
mutex_init(&tegra->lock);
|
|
tegra->dev = &pdev->dev;
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
|
|
if (IS_ERR(tegra->regs))
|
|
return PTR_ERR(tegra->regs);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(tegra->fpci_base))
|
|
return PTR_ERR(tegra->fpci_base);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
|
tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(tegra->ipfs_base))
|
|
return PTR_ERR(tegra->ipfs_base);
|
|
|
|
tegra->xhci_irq = platform_get_irq(pdev, 0);
|
|
if (tegra->xhci_irq < 0)
|
|
return tegra->xhci_irq;
|
|
|
|
tegra->mbox_irq = platform_get_irq(pdev, 1);
|
|
if (tegra->mbox_irq < 0)
|
|
return tegra->mbox_irq;
|
|
|
|
tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
|
|
if (IS_ERR(tegra->padctl))
|
|
return PTR_ERR(tegra->padctl);
|
|
|
|
tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host");
|
|
if (IS_ERR(tegra->host_rst)) {
|
|
err = PTR_ERR(tegra->host_rst);
|
|
dev_err(&pdev->dev, "failed to get xusb_host reset: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
|
|
if (IS_ERR(tegra->ss_rst)) {
|
|
err = PTR_ERR(tegra->ss_rst);
|
|
dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
|
|
if (IS_ERR(tegra->host_clk)) {
|
|
err = PTR_ERR(tegra->host_clk);
|
|
dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
|
|
if (IS_ERR(tegra->falcon_clk)) {
|
|
err = PTR_ERR(tegra->falcon_clk);
|
|
dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
|
|
if (IS_ERR(tegra->ss_clk)) {
|
|
err = PTR_ERR(tegra->ss_clk);
|
|
dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
|
|
if (IS_ERR(tegra->ss_src_clk)) {
|
|
err = PTR_ERR(tegra->ss_src_clk);
|
|
dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
|
|
if (IS_ERR(tegra->hs_src_clk)) {
|
|
err = PTR_ERR(tegra->hs_src_clk);
|
|
dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
|
|
if (IS_ERR(tegra->fs_src_clk)) {
|
|
err = PTR_ERR(tegra->fs_src_clk);
|
|
dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
|
|
if (IS_ERR(tegra->pll_u_480m)) {
|
|
err = PTR_ERR(tegra->pll_u_480m);
|
|
dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
|
|
if (IS_ERR(tegra->clk_m)) {
|
|
err = PTR_ERR(tegra->clk_m);
|
|
dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
|
|
if (IS_ERR(tegra->pll_e)) {
|
|
err = PTR_ERR(tegra->pll_e);
|
|
dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
|
|
sizeof(*tegra->supplies), GFP_KERNEL);
|
|
if (!tegra->supplies) {
|
|
err = -ENOMEM;
|
|
goto put_padctl;
|
|
}
|
|
|
|
for (i = 0; i < tegra->soc->num_supplies; i++)
|
|
tegra->supplies[i].supply = tegra->soc->supply_names[i];
|
|
|
|
err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
|
|
tegra->supplies);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
for (i = 0; i < tegra->soc->num_types; i++)
|
|
tegra->num_phys += tegra->soc->phy_types[i].num;
|
|
|
|
tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
|
|
sizeof(*tegra->phys), GFP_KERNEL);
|
|
if (!tegra->phys) {
|
|
dev_err(&pdev->dev, "failed to allocate PHY array\n");
|
|
err = -ENOMEM;
|
|
goto put_padctl;
|
|
}
|
|
|
|
for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
|
|
char prop[8];
|
|
|
|
for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
|
|
snprintf(prop, sizeof(prop), "%s-%d",
|
|
tegra->soc->phy_types[i].name, j);
|
|
|
|
phy = devm_phy_optional_get(&pdev->dev, prop);
|
|
if (IS_ERR(phy)) {
|
|
dev_err(&pdev->dev,
|
|
"failed to get PHY %s: %ld\n", prop,
|
|
PTR_ERR(phy));
|
|
err = PTR_ERR(phy);
|
|
goto put_padctl;
|
|
}
|
|
|
|
tegra->phys[k++] = phy;
|
|
}
|
|
}
|
|
|
|
err = tegra_xusb_clk_enable(tegra);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to enable clocks: %d\n", err);
|
|
goto put_padctl;
|
|
}
|
|
|
|
err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to enable regulators: %d\n", err);
|
|
goto disable_clk;
|
|
}
|
|
|
|
err = tegra_xusb_phy_enable(tegra);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
|
|
goto disable_regulator;
|
|
}
|
|
|
|
tegra_xusb_ipfs_config(tegra, regs);
|
|
|
|
err = tegra_xusb_load_firmware(tegra);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
|
|
goto disable_phy;
|
|
}
|
|
|
|
tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
|
|
dev_name(&pdev->dev));
|
|
if (!tegra->hcd) {
|
|
err = -ENOMEM;
|
|
goto disable_phy;
|
|
}
|
|
|
|
/*
|
|
* This must happen after usb_create_hcd(), because usb_create_hcd()
|
|
* will overwrite the drvdata of the device with the hcd it creates.
|
|
*/
|
|
platform_set_drvdata(pdev, tegra);
|
|
|
|
tegra->hcd->regs = tegra->regs;
|
|
tegra->hcd->rsrc_start = regs->start;
|
|
tegra->hcd->rsrc_len = resource_size(regs);
|
|
|
|
err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
|
|
goto put_usb2;
|
|
}
|
|
|
|
device_wakeup_enable(tegra->hcd->self.controller);
|
|
|
|
xhci = hcd_to_xhci(tegra->hcd);
|
|
|
|
xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
|
|
&pdev->dev,
|
|
dev_name(&pdev->dev),
|
|
tegra->hcd);
|
|
if (!xhci->shared_hcd) {
|
|
dev_err(&pdev->dev, "failed to create shared HCD\n");
|
|
goto remove_usb2;
|
|
}
|
|
|
|
err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
|
|
goto put_usb3;
|
|
}
|
|
|
|
mutex_lock(&tegra->lock);
|
|
|
|
/* Enable firmware messages from controller. */
|
|
msg.cmd = MBOX_CMD_MSG_ENABLED;
|
|
msg.data = 0;
|
|
|
|
err = tegra_xusb_mbox_send(tegra, &msg);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
|
|
mutex_unlock(&tegra->lock);
|
|
goto remove_usb3;
|
|
}
|
|
|
|
mutex_unlock(&tegra->lock);
|
|
|
|
err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
|
|
tegra_xusb_mbox_irq,
|
|
tegra_xusb_mbox_thread, 0,
|
|
dev_name(&pdev->dev), tegra);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
|
|
goto remove_usb3;
|
|
}
|
|
|
|
return 0;
|
|
|
|
remove_usb3:
|
|
usb_remove_hcd(xhci->shared_hcd);
|
|
put_usb3:
|
|
usb_put_hcd(xhci->shared_hcd);
|
|
remove_usb2:
|
|
usb_remove_hcd(tegra->hcd);
|
|
put_usb2:
|
|
usb_put_hcd(tegra->hcd);
|
|
disable_phy:
|
|
tegra_xusb_phy_disable(tegra);
|
|
disable_regulator:
|
|
regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
|
|
disable_clk:
|
|
tegra_xusb_clk_disable(tegra);
|
|
put_padctl:
|
|
tegra_xusb_padctl_put(tegra->padctl);
|
|
return err;
|
|
}
|
|
|
|
static int tegra_xusb_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_xusb *tegra = platform_get_drvdata(pdev);
|
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
|
|
|
|
usb_remove_hcd(xhci->shared_hcd);
|
|
usb_put_hcd(xhci->shared_hcd);
|
|
usb_remove_hcd(tegra->hcd);
|
|
usb_put_hcd(tegra->hcd);
|
|
|
|
dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
|
|
tegra->fw.phys);
|
|
|
|
tegra_xusb_phy_disable(tegra);
|
|
regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
|
|
tegra_xusb_clk_disable(tegra);
|
|
|
|
tegra_xusb_padctl_put(tegra->padctl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int tegra_xusb_suspend(struct device *dev)
|
|
{
|
|
struct tegra_xusb *tegra = dev_get_drvdata(dev);
|
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
|
|
bool wakeup = device_may_wakeup(dev);
|
|
|
|
/* TODO: Powergate controller across suspend/resume. */
|
|
return xhci_suspend(xhci, wakeup);
|
|
}
|
|
|
|
static int tegra_xusb_resume(struct device *dev)
|
|
{
|
|
struct tegra_xusb *tegra = dev_get_drvdata(dev);
|
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
|
|
|
|
return xhci_resume(xhci, 0);
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops tegra_xusb_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
|
|
};
|
|
|
|
static const char * const tegra124_supply_names[] = {
|
|
"avddio-pex",
|
|
"dvddio-pex",
|
|
"avdd-usb",
|
|
"avdd-pll-utmip",
|
|
"avdd-pll-erefe",
|
|
"avdd-usb-ss-pll",
|
|
"hvdd-usb-ss",
|
|
"hvdd-usb-ss-pll-e",
|
|
};
|
|
|
|
static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
|
|
{ .name = "usb3", .num = 2, },
|
|
{ .name = "usb2", .num = 3, },
|
|
{ .name = "hsic", .num = 2, },
|
|
};
|
|
|
|
static const struct tegra_xusb_soc tegra124_soc = {
|
|
.firmware = "nvidia/tegra124/xusb.bin",
|
|
.supply_names = tegra124_supply_names,
|
|
.num_supplies = ARRAY_SIZE(tegra124_supply_names),
|
|
.phy_types = tegra124_phy_types,
|
|
.num_types = ARRAY_SIZE(tegra124_phy_types),
|
|
.ports = {
|
|
.usb2 = { .offset = 4, .count = 4, },
|
|
.hsic = { .offset = 6, .count = 2, },
|
|
.usb3 = { .offset = 0, .count = 2, },
|
|
},
|
|
.scale_ss_clock = true,
|
|
};
|
|
MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
|
|
|
|
static const char * const tegra210_supply_names[] = {
|
|
"dvddio-pex",
|
|
"hvddio-pex",
|
|
"avdd-usb",
|
|
"avdd-pll-utmip",
|
|
"avdd-pll-uerefe",
|
|
"dvdd-pex-pll",
|
|
"hvdd-pex-pll-e",
|
|
};
|
|
|
|
static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
|
|
{ .name = "usb3", .num = 4, },
|
|
{ .name = "usb2", .num = 4, },
|
|
{ .name = "hsic", .num = 1, },
|
|
};
|
|
|
|
static const struct tegra_xusb_soc tegra210_soc = {
|
|
.firmware = "nvidia/tegra210/xusb.bin",
|
|
.supply_names = tegra210_supply_names,
|
|
.num_supplies = ARRAY_SIZE(tegra210_supply_names),
|
|
.phy_types = tegra210_phy_types,
|
|
.num_types = ARRAY_SIZE(tegra210_phy_types),
|
|
.ports = {
|
|
.usb2 = { .offset = 4, .count = 4, },
|
|
.hsic = { .offset = 8, .count = 1, },
|
|
.usb3 = { .offset = 0, .count = 4, },
|
|
},
|
|
.scale_ss_clock = false,
|
|
};
|
|
MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
|
|
|
|
static const struct of_device_id tegra_xusb_of_match[] = {
|
|
{ .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
|
|
{ .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
|
|
|
|
static struct platform_driver tegra_xusb_driver = {
|
|
.probe = tegra_xusb_probe,
|
|
.remove = tegra_xusb_remove,
|
|
.driver = {
|
|
.name = "tegra-xusb",
|
|
.pm = &tegra_xusb_pm_ops,
|
|
.of_match_table = tegra_xusb_of_match,
|
|
},
|
|
};
|
|
|
|
static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
|
|
{
|
|
xhci->quirks |= XHCI_PLAT;
|
|
}
|
|
|
|
static int tegra_xhci_setup(struct usb_hcd *hcd)
|
|
{
|
|
return xhci_gen_setup(hcd, tegra_xhci_quirks);
|
|
}
|
|
|
|
static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
|
|
.extra_priv_size = sizeof(struct xhci_hcd),
|
|
.reset = tegra_xhci_setup,
|
|
};
|
|
|
|
static int __init tegra_xusb_init(void)
|
|
{
|
|
xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
|
|
|
|
return platform_driver_register(&tegra_xusb_driver);
|
|
}
|
|
module_init(tegra_xusb_init);
|
|
|
|
static void __exit tegra_xusb_exit(void)
|
|
{
|
|
platform_driver_unregister(&tegra_xusb_driver);
|
|
}
|
|
module_exit(tegra_xusb_exit);
|
|
|
|
MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
|
|
MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
|
|
MODULE_LICENSE("GPL v2");
|