bbf53b95ed
1. Increases the max limit of PLL input frequency on RL6231 shared support. 2. Add a new pll preset map. Signed-off-by: Derek Fang <derek.fang@realtek.com> Link: https://lore.kernel.org/r/1580970133-14089-1-git-send-email-derek.fang@realtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
33 lines
814 B
C
33 lines
814 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* rl6231.h - RL6231 class device shared support
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*
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* Copyright 2014 Realtek Semiconductor Corp.
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*
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* Author: Oder Chiou <oder_chiou@realtek.com>
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*/
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#ifndef __RL6231_H__
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#define __RL6231_H__
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#define RL6231_PLL_INP_MAX 50000000
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#define RL6231_PLL_INP_MIN 256000
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#define RL6231_PLL_N_MAX 0x1ff
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#define RL6231_PLL_K_MAX 0x1f
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#define RL6231_PLL_M_MAX 0xf
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struct rl6231_pll_code {
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bool m_bp; /* Indicates bypass m code or not. */
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int m_code;
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int n_code;
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int k_code;
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};
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int rl6231_calc_dmic_clk(int rate);
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int rl6231_pll_calc(const unsigned int freq_in,
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const unsigned int freq_out, struct rl6231_pll_code *pll_code);
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int rl6231_get_clk_info(int sclk, int rate);
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int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft);
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#endif /* __RL6231_H__ */
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