![Tony Lindgren](/assets/img/avatar_default.png)
I noticed that modprobe clk-twl6040 can fail after a cold boot with: abe_cm:clk:0010:0: failed to enable ... Unhandled fault: imprecise external abort (0x1406) at 0xbe896b20 WARNING: CPU: 1 PID: 29 at drivers/clk/clk.c:828 clk_core_disable_lock+0x18/0x24 ... (clk_core_disable_lock) from [<c0123534>] (_disable_clocks+0x18/0x90) (_disable_clocks) from [<c0124040>] (_idle+0x17c/0x244) (_idle) from [<c0125ad4>] (omap_hwmod_idle+0x24/0x44) (omap_hwmod_idle) from [<c053a038>] (sysc_runtime_suspend+0x48/0x108) (sysc_runtime_suspend) from [<c06084c4>] (__rpm_callback+0x144/0x1d8) (__rpm_callback) from [<c0608578>] (rpm_callback+0x20/0x80) (rpm_callback) from [<c0607034>] (rpm_suspend+0x120/0x694) (rpm_suspend) from [<c0607a78>] (__pm_runtime_idle+0x60/0x84) (__pm_runtime_idle) from [<c053aaf0>] (sysc_probe+0x874/0xf2c) (sysc_probe) from [<c05fecd4>] (platform_drv_probe+0x48/0x98) After searching around for a similar issue, I came across an earlier fix that never got merged upstream in the Android tree for glass-omap-xrr02. There is patch "MFD: twl6040-codec: Implement PDMCLK cold temp errata" by Misael Lopez Cruz <misael.lopez@ti.com>. Based on my observations, this fix is also needed when cold booting devices, and not just for deeper idle modes. Since we now have a clock driver for pdmclk, let's fix the issue in twl6040_pdmclk_prepare(). Cc: Misael Lopez Cruz <misael.lopez@ti.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
177 lines
4.3 KiB
C
177 lines
4.3 KiB
C
/*
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* TWL6040 clock module driver for OMAP4 McPDM functional clock
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*
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* Copyright (C) 2012 Texas Instruments Inc.
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* Peter Ujfalusi <peter.ujfalusi@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/twl6040.h>
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#include <linux/clk-provider.h>
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struct twl6040_pdmclk {
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struct twl6040 *twl6040;
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struct device *dev;
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struct clk_hw pdmclk_hw;
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int enabled;
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};
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static int twl6040_pdmclk_is_prepared(struct clk_hw *hw)
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{
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struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
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pdmclk_hw);
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return pdmclk->enabled;
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}
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static int twl6040_pdmclk_reset_one_clock(struct twl6040_pdmclk *pdmclk,
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unsigned int reg)
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{
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const u8 reset_mask = TWL6040_HPLLRST; /* Same for HPPLL and LPPLL */
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int ret;
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ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask);
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if (ret < 0)
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return ret;
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ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask);
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if (ret < 0)
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return ret;
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return 0;
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}
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/*
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* TWL6040A2 Phoenix Audio IC erratum #6: "PDM Clock Generation Issue At
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* Cold Temperature". This affects cold boot and deeper idle states it
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* seems. The workaround consists of resetting HPPLL and LPPLL.
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*/
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static int twl6040_pdmclk_quirk_reset_clocks(struct twl6040_pdmclk *pdmclk)
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{
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int ret;
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ret = twl6040_pdmclk_reset_one_clock(pdmclk, TWL6040_REG_HPPLLCTL);
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if (ret)
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return ret;
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ret = twl6040_pdmclk_reset_one_clock(pdmclk, TWL6040_REG_LPPLLCTL);
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if (ret)
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return ret;
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return 0;
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}
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static int twl6040_pdmclk_prepare(struct clk_hw *hw)
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{
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struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
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pdmclk_hw);
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int ret;
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ret = twl6040_power(pdmclk->twl6040, 1);
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if (ret)
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return ret;
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ret = twl6040_pdmclk_quirk_reset_clocks(pdmclk);
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if (ret)
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goto out_err;
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pdmclk->enabled = 1;
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return 0;
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out_err:
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dev_err(pdmclk->dev, "%s: error %i\n", __func__, ret);
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twl6040_power(pdmclk->twl6040, 0);
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return ret;
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}
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static void twl6040_pdmclk_unprepare(struct clk_hw *hw)
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{
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struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
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pdmclk_hw);
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int ret;
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ret = twl6040_power(pdmclk->twl6040, 0);
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if (!ret)
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pdmclk->enabled = 0;
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}
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static unsigned long twl6040_pdmclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
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pdmclk_hw);
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return twl6040_get_sysclk(pdmclk->twl6040);
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}
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static const struct clk_ops twl6040_pdmclk_ops = {
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.is_prepared = twl6040_pdmclk_is_prepared,
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.prepare = twl6040_pdmclk_prepare,
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.unprepare = twl6040_pdmclk_unprepare,
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.recalc_rate = twl6040_pdmclk_recalc_rate,
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};
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static const struct clk_init_data twl6040_pdmclk_init = {
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.name = "pdmclk",
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.ops = &twl6040_pdmclk_ops,
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.flags = CLK_GET_RATE_NOCACHE,
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};
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static int twl6040_pdmclk_probe(struct platform_device *pdev)
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{
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struct twl6040 *twl6040 = dev_get_drvdata(pdev->dev.parent);
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struct twl6040_pdmclk *clkdata;
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int ret;
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clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
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if (!clkdata)
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return -ENOMEM;
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clkdata->dev = &pdev->dev;
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clkdata->twl6040 = twl6040;
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clkdata->pdmclk_hw.init = &twl6040_pdmclk_init;
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ret = devm_clk_hw_register(&pdev->dev, &clkdata->pdmclk_hw);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, clkdata);
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return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
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&clkdata->pdmclk_hw);
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}
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static struct platform_driver twl6040_pdmclk_driver = {
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.driver = {
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.name = "twl6040-pdmclk",
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},
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.probe = twl6040_pdmclk_probe,
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};
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module_platform_driver(twl6040_pdmclk_driver);
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MODULE_DESCRIPTION("TWL6040 clock driver for McPDM functional clock");
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MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
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MODULE_ALIAS("platform:twl6040-pdmclk");
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MODULE_LICENSE("GPL");
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