![Rafael J. Wysocki](/assets/img/avatar_default.png)
* pm-opp: cpufreq: OMAP: Register an Energy Model cpufreq: imx6q: Register an Energy Model opp: no need to check return value of debugfs_create functions cpufreq: mediatek: Register an Energy Model cpufreq: scmi: Register an Energy Model cpufreq: arm_big_little: Register an Energy Model cpufreq: scpi: Register an Energy Model cpufreq: dt: Register an Energy Model
591 lines
15 KiB
C
591 lines
15 KiB
C
/*
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* Copyright (c) 2015 Linaro Ltd.
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* Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/cpumask.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/thermal.h>
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#define MIN_VOLT_SHIFT (100000)
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#define MAX_VOLT_SHIFT (200000)
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#define MAX_VOLT_LIMIT (1150000)
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#define VOLT_TOL (10000)
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/*
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* The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
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* on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
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* Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
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* voltage inputs need to be controlled under a hardware limitation:
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* 100mV < Vsram - Vproc < 200mV
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*
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* When scaling the clock frequency of a CPU clock domain, the clock source
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* needs to be switched to another stable PLL clock temporarily until
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* the original PLL becomes stable at target frequency.
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*/
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struct mtk_cpu_dvfs_info {
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struct cpumask cpus;
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struct device *cpu_dev;
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struct regulator *proc_reg;
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struct regulator *sram_reg;
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struct clk *cpu_clk;
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struct clk *inter_clk;
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struct list_head list_head;
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int intermediate_voltage;
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bool need_voltage_tracking;
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};
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static LIST_HEAD(dvfs_info_list);
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static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
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{
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struct mtk_cpu_dvfs_info *info;
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list_for_each_entry(info, &dvfs_info_list, list_head) {
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if (cpumask_test_cpu(cpu, &info->cpus))
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return info;
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}
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return NULL;
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}
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static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
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int new_vproc)
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{
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struct regulator *proc_reg = info->proc_reg;
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struct regulator *sram_reg = info->sram_reg;
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int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
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old_vproc = regulator_get_voltage(proc_reg);
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if (old_vproc < 0) {
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pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
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return old_vproc;
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}
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/* Vsram should not exceed the maximum allowed voltage of SoC. */
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new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
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if (old_vproc < new_vproc) {
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/*
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* When scaling up voltages, Vsram and Vproc scale up step
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* by step. At each step, set Vsram to (Vproc + 200mV) first,
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* then set Vproc to (Vsram - 100mV).
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* Keep doing it until Vsram and Vproc hit target voltages.
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*/
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do {
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old_vsram = regulator_get_voltage(sram_reg);
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if (old_vsram < 0) {
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pr_err("%s: invalid Vsram value: %d\n",
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__func__, old_vsram);
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return old_vsram;
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}
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old_vproc = regulator_get_voltage(proc_reg);
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if (old_vproc < 0) {
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pr_err("%s: invalid Vproc value: %d\n",
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__func__, old_vproc);
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return old_vproc;
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}
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vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT);
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if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
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vsram = MAX_VOLT_LIMIT;
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/*
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* If the target Vsram hits the maximum voltage,
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* try to set the exact voltage value first.
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*/
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ret = regulator_set_voltage(sram_reg, vsram,
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vsram);
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if (ret)
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ret = regulator_set_voltage(sram_reg,
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vsram - VOLT_TOL,
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vsram);
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vproc = new_vproc;
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} else {
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ret = regulator_set_voltage(sram_reg, vsram,
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vsram + VOLT_TOL);
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vproc = vsram - MIN_VOLT_SHIFT;
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}
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if (ret)
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return ret;
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ret = regulator_set_voltage(proc_reg, vproc,
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vproc + VOLT_TOL);
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if (ret) {
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regulator_set_voltage(sram_reg, old_vsram,
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old_vsram);
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return ret;
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}
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} while (vproc < new_vproc || vsram < new_vsram);
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} else if (old_vproc > new_vproc) {
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/*
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* When scaling down voltages, Vsram and Vproc scale down step
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* by step. At each step, set Vproc to (Vsram - 200mV) first,
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* then set Vproc to (Vproc + 100mV).
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* Keep doing it until Vsram and Vproc hit target voltages.
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*/
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do {
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old_vproc = regulator_get_voltage(proc_reg);
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if (old_vproc < 0) {
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pr_err("%s: invalid Vproc value: %d\n",
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__func__, old_vproc);
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return old_vproc;
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}
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old_vsram = regulator_get_voltage(sram_reg);
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if (old_vsram < 0) {
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pr_err("%s: invalid Vsram value: %d\n",
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__func__, old_vsram);
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return old_vsram;
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}
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vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT);
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ret = regulator_set_voltage(proc_reg, vproc,
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vproc + VOLT_TOL);
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if (ret)
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return ret;
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if (vproc == new_vproc)
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vsram = new_vsram;
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else
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vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
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if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
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vsram = MAX_VOLT_LIMIT;
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/*
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* If the target Vsram hits the maximum voltage,
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* try to set the exact voltage value first.
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*/
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ret = regulator_set_voltage(sram_reg, vsram,
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vsram);
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if (ret)
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ret = regulator_set_voltage(sram_reg,
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vsram - VOLT_TOL,
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vsram);
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} else {
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ret = regulator_set_voltage(sram_reg, vsram,
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vsram + VOLT_TOL);
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}
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if (ret) {
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regulator_set_voltage(proc_reg, old_vproc,
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old_vproc);
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return ret;
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}
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} while (vproc > new_vproc + VOLT_TOL ||
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vsram > new_vsram + VOLT_TOL);
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}
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return 0;
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}
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static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
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{
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if (info->need_voltage_tracking)
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return mtk_cpufreq_voltage_tracking(info, vproc);
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else
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return regulator_set_voltage(info->proc_reg, vproc,
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vproc + VOLT_TOL);
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}
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static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct cpufreq_frequency_table *freq_table = policy->freq_table;
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struct clk *cpu_clk = policy->clk;
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struct clk *armpll = clk_get_parent(cpu_clk);
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struct mtk_cpu_dvfs_info *info = policy->driver_data;
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struct device *cpu_dev = info->cpu_dev;
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struct dev_pm_opp *opp;
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long freq_hz, old_freq_hz;
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int vproc, old_vproc, inter_vproc, target_vproc, ret;
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inter_vproc = info->intermediate_voltage;
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old_freq_hz = clk_get_rate(cpu_clk);
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old_vproc = regulator_get_voltage(info->proc_reg);
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if (old_vproc < 0) {
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pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
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return old_vproc;
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}
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freq_hz = freq_table[index].frequency * 1000;
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
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if (IS_ERR(opp)) {
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pr_err("cpu%d: failed to find OPP for %ld\n",
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policy->cpu, freq_hz);
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return PTR_ERR(opp);
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}
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vproc = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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/*
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* If the new voltage or the intermediate voltage is higher than the
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* current voltage, scale up voltage first.
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*/
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target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
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if (old_vproc < target_vproc) {
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ret = mtk_cpufreq_set_voltage(info, target_vproc);
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if (ret) {
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pr_err("cpu%d: failed to scale up voltage!\n",
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policy->cpu);
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mtk_cpufreq_set_voltage(info, old_vproc);
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return ret;
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}
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}
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/* Reparent the CPU clock to intermediate clock. */
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ret = clk_set_parent(cpu_clk, info->inter_clk);
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if (ret) {
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pr_err("cpu%d: failed to re-parent cpu clock!\n",
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policy->cpu);
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mtk_cpufreq_set_voltage(info, old_vproc);
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WARN_ON(1);
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return ret;
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}
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/* Set the original PLL to target rate. */
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ret = clk_set_rate(armpll, freq_hz);
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if (ret) {
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pr_err("cpu%d: failed to scale cpu clock rate!\n",
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policy->cpu);
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clk_set_parent(cpu_clk, armpll);
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mtk_cpufreq_set_voltage(info, old_vproc);
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return ret;
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}
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/* Set parent of CPU clock back to the original PLL. */
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ret = clk_set_parent(cpu_clk, armpll);
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if (ret) {
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pr_err("cpu%d: failed to re-parent cpu clock!\n",
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policy->cpu);
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mtk_cpufreq_set_voltage(info, inter_vproc);
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WARN_ON(1);
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return ret;
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}
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/*
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* If the new voltage is lower than the intermediate voltage or the
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* original voltage, scale down to the new voltage.
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*/
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if (vproc < inter_vproc || vproc < old_vproc) {
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ret = mtk_cpufreq_set_voltage(info, vproc);
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if (ret) {
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pr_err("cpu%d: failed to scale down voltage!\n",
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policy->cpu);
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clk_set_parent(cpu_clk, info->inter_clk);
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clk_set_rate(armpll, old_freq_hz);
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clk_set_parent(cpu_clk, armpll);
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return ret;
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}
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}
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return 0;
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}
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#define DYNAMIC_POWER "dynamic-power-coefficient"
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static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
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{
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struct device *cpu_dev;
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struct regulator *proc_reg = ERR_PTR(-ENODEV);
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struct regulator *sram_reg = ERR_PTR(-ENODEV);
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struct clk *cpu_clk = ERR_PTR(-ENODEV);
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struct clk *inter_clk = ERR_PTR(-ENODEV);
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struct dev_pm_opp *opp;
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unsigned long rate;
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int ret;
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cpu_dev = get_cpu_device(cpu);
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if (!cpu_dev) {
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pr_err("failed to get cpu%d device\n", cpu);
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return -ENODEV;
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}
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cpu_clk = clk_get(cpu_dev, "cpu");
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if (IS_ERR(cpu_clk)) {
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if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
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pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
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else
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pr_err("failed to get cpu clk for cpu%d\n", cpu);
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ret = PTR_ERR(cpu_clk);
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return ret;
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}
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inter_clk = clk_get(cpu_dev, "intermediate");
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if (IS_ERR(inter_clk)) {
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if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
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pr_warn("intermediate clk for cpu%d not ready, retry.\n",
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cpu);
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else
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pr_err("failed to get intermediate clk for cpu%d\n",
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cpu);
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ret = PTR_ERR(inter_clk);
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goto out_free_resources;
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}
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proc_reg = regulator_get_exclusive(cpu_dev, "proc");
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if (IS_ERR(proc_reg)) {
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if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
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pr_warn("proc regulator for cpu%d not ready, retry.\n",
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cpu);
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else
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pr_err("failed to get proc regulator for cpu%d\n",
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cpu);
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ret = PTR_ERR(proc_reg);
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goto out_free_resources;
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}
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/* Both presence and absence of sram regulator are valid cases. */
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sram_reg = regulator_get_exclusive(cpu_dev, "sram");
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/* Get OPP-sharing information from "operating-points-v2" bindings */
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ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
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if (ret) {
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pr_err("failed to get OPP-sharing information for cpu%d\n",
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cpu);
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goto out_free_resources;
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}
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ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
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if (ret) {
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pr_warn("no OPP table for cpu%d\n", cpu);
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goto out_free_resources;
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}
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/* Search a safe voltage for intermediate frequency. */
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rate = clk_get_rate(inter_clk);
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
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if (IS_ERR(opp)) {
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pr_err("failed to get intermediate opp for cpu%d\n", cpu);
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ret = PTR_ERR(opp);
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goto out_free_opp_table;
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}
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info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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info->cpu_dev = cpu_dev;
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info->proc_reg = proc_reg;
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info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
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info->cpu_clk = cpu_clk;
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info->inter_clk = inter_clk;
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/*
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* If SRAM regulator is present, software "voltage tracking" is needed
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* for this CPU power domain.
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*/
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info->need_voltage_tracking = !IS_ERR(sram_reg);
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return 0;
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out_free_opp_table:
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dev_pm_opp_of_cpumask_remove_table(&info->cpus);
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out_free_resources:
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if (!IS_ERR(proc_reg))
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regulator_put(proc_reg);
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if (!IS_ERR(sram_reg))
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regulator_put(sram_reg);
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if (!IS_ERR(cpu_clk))
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clk_put(cpu_clk);
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if (!IS_ERR(inter_clk))
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clk_put(inter_clk);
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return ret;
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}
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static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
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{
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if (!IS_ERR(info->proc_reg))
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regulator_put(info->proc_reg);
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if (!IS_ERR(info->sram_reg))
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regulator_put(info->sram_reg);
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if (!IS_ERR(info->cpu_clk))
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clk_put(info->cpu_clk);
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if (!IS_ERR(info->inter_clk))
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clk_put(info->inter_clk);
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dev_pm_opp_of_cpumask_remove_table(&info->cpus);
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}
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static int mtk_cpufreq_init(struct cpufreq_policy *policy)
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{
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struct mtk_cpu_dvfs_info *info;
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struct cpufreq_frequency_table *freq_table;
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int ret;
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info = mtk_cpu_dvfs_info_lookup(policy->cpu);
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if (!info) {
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pr_err("dvfs info for cpu%d is not initialized.\n",
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policy->cpu);
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return -EINVAL;
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}
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ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
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if (ret) {
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pr_err("failed to init cpufreq table for cpu%d: %d\n",
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policy->cpu, ret);
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return ret;
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}
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cpumask_copy(policy->cpus, &info->cpus);
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policy->freq_table = freq_table;
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policy->driver_data = info;
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policy->clk = info->cpu_clk;
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dev_pm_opp_of_register_em(policy->cpus);
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return 0;
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}
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static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
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{
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struct mtk_cpu_dvfs_info *info = policy->driver_data;
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dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
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return 0;
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}
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static struct cpufreq_driver mtk_cpufreq_driver = {
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.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
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CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
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CPUFREQ_IS_COOLING_DEV,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = mtk_cpufreq_set_target,
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.get = cpufreq_generic_get,
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.init = mtk_cpufreq_init,
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.exit = mtk_cpufreq_exit,
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.name = "mtk-cpufreq",
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.attr = cpufreq_generic_attr,
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};
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static int mtk_cpufreq_probe(struct platform_device *pdev)
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|
{
|
|
struct mtk_cpu_dvfs_info *info, *tmp;
|
|
int cpu, ret;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
info = mtk_cpu_dvfs_info_lookup(cpu);
|
|
if (info)
|
|
continue;
|
|
|
|
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
|
|
if (!info) {
|
|
ret = -ENOMEM;
|
|
goto release_dvfs_info_list;
|
|
}
|
|
|
|
ret = mtk_cpu_dvfs_info_init(info, cpu);
|
|
if (ret) {
|
|
dev_err(&pdev->dev,
|
|
"failed to initialize dvfs info for cpu%d\n",
|
|
cpu);
|
|
goto release_dvfs_info_list;
|
|
}
|
|
|
|
list_add(&info->list_head, &dvfs_info_list);
|
|
}
|
|
|
|
ret = cpufreq_register_driver(&mtk_cpufreq_driver);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to register mtk cpufreq driver\n");
|
|
goto release_dvfs_info_list;
|
|
}
|
|
|
|
return 0;
|
|
|
|
release_dvfs_info_list:
|
|
list_for_each_entry_safe(info, tmp, &dvfs_info_list, list_head) {
|
|
mtk_cpu_dvfs_info_release(info);
|
|
list_del(&info->list_head);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver mtk_cpufreq_platdrv = {
|
|
.driver = {
|
|
.name = "mtk-cpufreq",
|
|
},
|
|
.probe = mtk_cpufreq_probe,
|
|
};
|
|
|
|
/* List of machines supported by this driver */
|
|
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
|
|
{ .compatible = "mediatek,mt2701", },
|
|
{ .compatible = "mediatek,mt2712", },
|
|
{ .compatible = "mediatek,mt7622", },
|
|
{ .compatible = "mediatek,mt7623", },
|
|
{ .compatible = "mediatek,mt817x", },
|
|
{ .compatible = "mediatek,mt8173", },
|
|
{ .compatible = "mediatek,mt8176", },
|
|
|
|
{ }
|
|
};
|
|
|
|
static int __init mtk_cpufreq_driver_init(void)
|
|
{
|
|
struct device_node *np;
|
|
const struct of_device_id *match;
|
|
struct platform_device *pdev;
|
|
int err;
|
|
|
|
np = of_find_node_by_path("/");
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
match = of_match_node(mtk_cpufreq_machines, np);
|
|
of_node_put(np);
|
|
if (!match) {
|
|
pr_debug("Machine is not compatible with mtk-cpufreq\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
err = platform_driver_register(&mtk_cpufreq_platdrv);
|
|
if (err)
|
|
return err;
|
|
|
|
/*
|
|
* Since there's no place to hold device registration code and no
|
|
* device tree based way to match cpufreq driver yet, both the driver
|
|
* and the device registration codes are put here to handle defer
|
|
* probing.
|
|
*/
|
|
pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
|
|
if (IS_ERR(pdev)) {
|
|
pr_err("failed to register mtk-cpufreq platform device\n");
|
|
return PTR_ERR(pdev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
device_initcall(mtk_cpufreq_driver_init);
|
|
|
|
MODULE_DESCRIPTION("MediaTek CPUFreq driver");
|
|
MODULE_AUTHOR("Pi-Cheng Chen <pi-cheng.chen@linaro.org>");
|
|
MODULE_LICENSE("GPL v2");
|