![Fabien Dessenne](/assets/img/avatar_default.png)
Manage the -EPROBE_DEFER error case for the wake IRQ. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
936 lines
24 KiB
C
936 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2017
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* Author: Amelie Delaunay <amelie.delaunay@st.com>
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*/
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#include <linux/bcd.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/regmap.h>
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#include <linux/rtc.h>
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#define DRIVER_NAME "stm32_rtc"
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/* STM32_RTC_TR bit fields */
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#define STM32_RTC_TR_SEC_SHIFT 0
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#define STM32_RTC_TR_SEC GENMASK(6, 0)
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#define STM32_RTC_TR_MIN_SHIFT 8
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#define STM32_RTC_TR_MIN GENMASK(14, 8)
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#define STM32_RTC_TR_HOUR_SHIFT 16
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#define STM32_RTC_TR_HOUR GENMASK(21, 16)
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/* STM32_RTC_DR bit fields */
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#define STM32_RTC_DR_DATE_SHIFT 0
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#define STM32_RTC_DR_DATE GENMASK(5, 0)
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#define STM32_RTC_DR_MONTH_SHIFT 8
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#define STM32_RTC_DR_MONTH GENMASK(12, 8)
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#define STM32_RTC_DR_WDAY_SHIFT 13
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#define STM32_RTC_DR_WDAY GENMASK(15, 13)
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#define STM32_RTC_DR_YEAR_SHIFT 16
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#define STM32_RTC_DR_YEAR GENMASK(23, 16)
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/* STM32_RTC_CR bit fields */
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#define STM32_RTC_CR_FMT BIT(6)
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#define STM32_RTC_CR_ALRAE BIT(8)
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#define STM32_RTC_CR_ALRAIE BIT(12)
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/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
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#define STM32_RTC_ISR_ALRAWF BIT(0)
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#define STM32_RTC_ISR_INITS BIT(4)
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#define STM32_RTC_ISR_RSF BIT(5)
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#define STM32_RTC_ISR_INITF BIT(6)
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#define STM32_RTC_ISR_INIT BIT(7)
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#define STM32_RTC_ISR_ALRAF BIT(8)
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/* STM32_RTC_PRER bit fields */
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#define STM32_RTC_PRER_PRED_S_SHIFT 0
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#define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
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#define STM32_RTC_PRER_PRED_A_SHIFT 16
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#define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
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/* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
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#define STM32_RTC_ALRMXR_SEC_SHIFT 0
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#define STM32_RTC_ALRMXR_SEC GENMASK(6, 0)
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#define STM32_RTC_ALRMXR_SEC_MASK BIT(7)
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#define STM32_RTC_ALRMXR_MIN_SHIFT 8
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#define STM32_RTC_ALRMXR_MIN GENMASK(14, 8)
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#define STM32_RTC_ALRMXR_MIN_MASK BIT(15)
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#define STM32_RTC_ALRMXR_HOUR_SHIFT 16
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#define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16)
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#define STM32_RTC_ALRMXR_PM BIT(22)
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#define STM32_RTC_ALRMXR_HOUR_MASK BIT(23)
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#define STM32_RTC_ALRMXR_DATE_SHIFT 24
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#define STM32_RTC_ALRMXR_DATE GENMASK(29, 24)
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#define STM32_RTC_ALRMXR_WDSEL BIT(30)
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#define STM32_RTC_ALRMXR_WDAY_SHIFT 24
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#define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
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#define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
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/* STM32_RTC_SR/_SCR bit fields */
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#define STM32_RTC_SR_ALRA BIT(0)
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/* STM32_RTC_VERR bit fields */
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#define STM32_RTC_VERR_MINREV_SHIFT 0
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#define STM32_RTC_VERR_MINREV GENMASK(3, 0)
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#define STM32_RTC_VERR_MAJREV_SHIFT 4
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#define STM32_RTC_VERR_MAJREV GENMASK(7, 4)
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/* STM32_RTC_WPR key constants */
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#define RTC_WPR_1ST_KEY 0xCA
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#define RTC_WPR_2ND_KEY 0x53
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#define RTC_WPR_WRONG_KEY 0xFF
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/* Max STM32 RTC register offset is 0x3FC */
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#define UNDEF_REG 0xFFFF
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struct stm32_rtc;
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struct stm32_rtc_registers {
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u16 tr;
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u16 dr;
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u16 cr;
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u16 isr;
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u16 prer;
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u16 alrmar;
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u16 wpr;
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u16 sr;
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u16 scr;
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u16 verr;
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};
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struct stm32_rtc_events {
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u32 alra;
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};
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struct stm32_rtc_data {
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const struct stm32_rtc_registers regs;
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const struct stm32_rtc_events events;
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void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
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bool has_pclk;
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bool need_dbp;
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bool has_wakeirq;
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};
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struct stm32_rtc {
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struct rtc_device *rtc_dev;
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void __iomem *base;
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struct regmap *dbp;
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unsigned int dbp_reg;
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unsigned int dbp_mask;
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struct clk *pclk;
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struct clk *rtc_ck;
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const struct stm32_rtc_data *data;
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int irq_alarm;
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int wakeirq_alarm;
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};
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static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
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writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
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}
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static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
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}
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static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int isr = readl_relaxed(rtc->base + regs->isr);
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if (!(isr & STM32_RTC_ISR_INITF)) {
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isr |= STM32_RTC_ISR_INIT;
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writel_relaxed(isr, rtc->base + regs->isr);
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/*
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* It takes around 2 rtc_ck clock cycles to enter in
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* initialization phase mode (and have INITF flag set). As
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* slowest rtc_ck frequency may be 32kHz and highest should be
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* 1MHz, we poll every 10 us with a timeout of 100ms.
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*/
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return readl_relaxed_poll_timeout_atomic(
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rtc->base + regs->isr,
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isr, (isr & STM32_RTC_ISR_INITF),
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10, 100000);
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}
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return 0;
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}
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static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int isr = readl_relaxed(rtc->base + regs->isr);
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isr &= ~STM32_RTC_ISR_INIT;
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writel_relaxed(isr, rtc->base + regs->isr);
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}
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static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int isr = readl_relaxed(rtc->base + regs->isr);
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isr &= ~STM32_RTC_ISR_RSF;
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writel_relaxed(isr, rtc->base + regs->isr);
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/*
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* Wait for RSF to be set to ensure the calendar registers are
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* synchronised, it takes around 2 rtc_ck clock cycles
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*/
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return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
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isr,
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(isr & STM32_RTC_ISR_RSF),
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10, 100000);
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}
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static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
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unsigned int flags)
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{
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rtc->data->clear_events(rtc, flags);
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}
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static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
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{
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struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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const struct stm32_rtc_events *evts = &rtc->data->events;
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unsigned int status, cr;
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mutex_lock(&rtc->rtc_dev->ops_lock);
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status = readl_relaxed(rtc->base + regs->sr);
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cr = readl_relaxed(rtc->base + regs->cr);
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if ((status & evts->alra) &&
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(cr & STM32_RTC_CR_ALRAIE)) {
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/* Alarm A flag - Alarm interrupt */
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dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
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/* Pass event to the kernel */
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rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
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/* Clear event flags, otherwise new events won't be received */
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stm32_rtc_clear_event_flags(rtc, evts->alra);
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}
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mutex_unlock(&rtc->rtc_dev->ops_lock);
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return IRQ_HANDLED;
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}
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/* Convert rtc_time structure from bin to bcd format */
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static void tm2bcd(struct rtc_time *tm)
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{
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tm->tm_sec = bin2bcd(tm->tm_sec);
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tm->tm_min = bin2bcd(tm->tm_min);
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tm->tm_hour = bin2bcd(tm->tm_hour);
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tm->tm_mday = bin2bcd(tm->tm_mday);
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tm->tm_mon = bin2bcd(tm->tm_mon + 1);
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tm->tm_year = bin2bcd(tm->tm_year - 100);
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/*
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* Number of days since Sunday
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* - on kernel side, 0=Sunday...6=Saturday
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* - on rtc side, 0=invalid,1=Monday...7=Sunday
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*/
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tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
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}
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/* Convert rtc_time structure from bcd to bin format */
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static void bcd2tm(struct rtc_time *tm)
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{
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tm->tm_sec = bcd2bin(tm->tm_sec);
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tm->tm_min = bcd2bin(tm->tm_min);
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tm->tm_hour = bcd2bin(tm->tm_hour);
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tm->tm_mday = bcd2bin(tm->tm_mday);
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tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
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tm->tm_year = bcd2bin(tm->tm_year) + 100;
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/*
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* Number of days since Sunday
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* - on kernel side, 0=Sunday...6=Saturday
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* - on rtc side, 0=invalid,1=Monday...7=Sunday
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*/
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tm->tm_wday %= 7;
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}
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static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int tr, dr;
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/* Time and Date in BCD format */
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tr = readl_relaxed(rtc->base + regs->tr);
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dr = readl_relaxed(rtc->base + regs->dr);
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tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
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tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
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tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
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tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
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tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
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tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
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tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
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/* We don't report tm_yday and tm_isdst */
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bcd2tm(tm);
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return 0;
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}
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static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int tr, dr;
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int ret = 0;
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tm2bcd(tm);
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/* Time in BCD format */
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tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
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((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
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((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
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/* Date in BCD format */
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dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
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((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
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((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
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((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
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stm32_rtc_wpr_unlock(rtc);
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ret = stm32_rtc_enter_init_mode(rtc);
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if (ret) {
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dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
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goto end;
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}
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writel_relaxed(tr, rtc->base + regs->tr);
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writel_relaxed(dr, rtc->base + regs->dr);
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stm32_rtc_exit_init_mode(rtc);
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ret = stm32_rtc_wait_sync(rtc);
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end:
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stm32_rtc_wpr_lock(rtc);
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return ret;
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}
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static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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const struct stm32_rtc_events *evts = &rtc->data->events;
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struct rtc_time *tm = &alrm->time;
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unsigned int alrmar, cr, status;
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alrmar = readl_relaxed(rtc->base + regs->alrmar);
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cr = readl_relaxed(rtc->base + regs->cr);
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status = readl_relaxed(rtc->base + regs->sr);
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if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
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/*
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* Date/day doesn't matter in Alarm comparison so alarm
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* triggers every day
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*/
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tm->tm_mday = -1;
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tm->tm_wday = -1;
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} else {
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if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
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/* Alarm is set to a day of week */
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tm->tm_mday = -1;
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tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
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STM32_RTC_ALRMXR_WDAY_SHIFT;
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tm->tm_wday %= 7;
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} else {
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/* Alarm is set to a day of month */
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tm->tm_wday = -1;
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tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
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STM32_RTC_ALRMXR_DATE_SHIFT;
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}
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}
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if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
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/* Hours don't matter in Alarm comparison */
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tm->tm_hour = -1;
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} else {
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tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
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STM32_RTC_ALRMXR_HOUR_SHIFT;
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if (alrmar & STM32_RTC_ALRMXR_PM)
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tm->tm_hour += 12;
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}
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if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
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/* Minutes don't matter in Alarm comparison */
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tm->tm_min = -1;
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} else {
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tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
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STM32_RTC_ALRMXR_MIN_SHIFT;
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}
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if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
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/* Seconds don't matter in Alarm comparison */
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tm->tm_sec = -1;
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} else {
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tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
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STM32_RTC_ALRMXR_SEC_SHIFT;
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}
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bcd2tm(tm);
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alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
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alrm->pending = (status & evts->alra) ? 1 : 0;
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return 0;
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}
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static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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const struct stm32_rtc_events *evts = &rtc->data->events;
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unsigned int cr;
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cr = readl_relaxed(rtc->base + regs->cr);
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stm32_rtc_wpr_unlock(rtc);
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/* We expose Alarm A to the kernel */
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if (enabled)
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cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
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else
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cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
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writel_relaxed(cr, rtc->base + regs->cr);
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/* Clear event flags, otherwise new events won't be received */
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stm32_rtc_clear_event_flags(rtc, evts->alra);
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stm32_rtc_wpr_lock(rtc);
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return 0;
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}
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static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
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unsigned int dr = readl_relaxed(rtc->base + regs->dr);
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unsigned int tr = readl_relaxed(rtc->base + regs->tr);
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cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
|
|
cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
|
|
cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
|
|
cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
|
|
cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
|
|
cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
|
|
|
|
/*
|
|
* Assuming current date is M-D-Y H:M:S.
|
|
* RTC alarm can't be set on a specific month and year.
|
|
* So the valid alarm range is:
|
|
* M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
|
|
* with a specific case for December...
|
|
*/
|
|
if ((((tm->tm_year > cur_year) &&
|
|
(tm->tm_mon == 0x1) && (cur_mon == 0x12)) ||
|
|
((tm->tm_year == cur_year) &&
|
|
(tm->tm_mon <= cur_mon + 1))) &&
|
|
((tm->tm_mday > cur_day) ||
|
|
((tm->tm_mday == cur_day) &&
|
|
((tm->tm_hour > cur_hour) ||
|
|
((tm->tm_hour == cur_hour) && (tm->tm_min > cur_min)) ||
|
|
((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) &&
|
|
(tm->tm_sec >= cur_sec))))))
|
|
return 0;
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
|
|
{
|
|
struct stm32_rtc *rtc = dev_get_drvdata(dev);
|
|
const struct stm32_rtc_registers *regs = &rtc->data->regs;
|
|
struct rtc_time *tm = &alrm->time;
|
|
unsigned int cr, isr, alrmar;
|
|
int ret = 0;
|
|
|
|
tm2bcd(tm);
|
|
|
|
/*
|
|
* RTC alarm can't be set on a specific date, unless this date is
|
|
* up to the same day of month next month.
|
|
*/
|
|
if (stm32_rtc_valid_alrm(rtc, tm) < 0) {
|
|
dev_err(dev, "Alarm can be set only on upcoming month.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
alrmar = 0;
|
|
/* tm_year and tm_mon are not used because not supported by RTC */
|
|
alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
|
|
STM32_RTC_ALRMXR_DATE;
|
|
/* 24-hour format */
|
|
alrmar &= ~STM32_RTC_ALRMXR_PM;
|
|
alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
|
|
STM32_RTC_ALRMXR_HOUR;
|
|
alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
|
|
STM32_RTC_ALRMXR_MIN;
|
|
alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
|
|
STM32_RTC_ALRMXR_SEC;
|
|
|
|
stm32_rtc_wpr_unlock(rtc);
|
|
|
|
/* Disable Alarm */
|
|
cr = readl_relaxed(rtc->base + regs->cr);
|
|
cr &= ~STM32_RTC_CR_ALRAE;
|
|
writel_relaxed(cr, rtc->base + regs->cr);
|
|
|
|
/*
|
|
* Poll Alarm write flag to be sure that Alarm update is allowed: it
|
|
* takes around 2 rtc_ck clock cycles
|
|
*/
|
|
ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
|
|
isr,
|
|
(isr & STM32_RTC_ISR_ALRAWF),
|
|
10, 100000);
|
|
|
|
if (ret) {
|
|
dev_err(dev, "Alarm update not allowed\n");
|
|
goto end;
|
|
}
|
|
|
|
/* Write to Alarm register */
|
|
writel_relaxed(alrmar, rtc->base + regs->alrmar);
|
|
|
|
if (alrm->enabled)
|
|
stm32_rtc_alarm_irq_enable(dev, 1);
|
|
else
|
|
stm32_rtc_alarm_irq_enable(dev, 0);
|
|
|
|
end:
|
|
stm32_rtc_wpr_lock(rtc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct rtc_class_ops stm32_rtc_ops = {
|
|
.read_time = stm32_rtc_read_time,
|
|
.set_time = stm32_rtc_set_time,
|
|
.read_alarm = stm32_rtc_read_alarm,
|
|
.set_alarm = stm32_rtc_set_alarm,
|
|
.alarm_irq_enable = stm32_rtc_alarm_irq_enable,
|
|
};
|
|
|
|
static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
|
|
unsigned int flags)
|
|
{
|
|
const struct stm32_rtc_registers *regs = &rtc->data->regs;
|
|
|
|
/* Flags are cleared by writing 0 in RTC_ISR */
|
|
writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
|
|
rtc->base + regs->isr);
|
|
}
|
|
|
|
static const struct stm32_rtc_data stm32_rtc_data = {
|
|
.has_pclk = false,
|
|
.need_dbp = true,
|
|
.has_wakeirq = false,
|
|
.regs = {
|
|
.tr = 0x00,
|
|
.dr = 0x04,
|
|
.cr = 0x08,
|
|
.isr = 0x0C,
|
|
.prer = 0x10,
|
|
.alrmar = 0x1C,
|
|
.wpr = 0x24,
|
|
.sr = 0x0C, /* set to ISR offset to ease alarm management */
|
|
.scr = UNDEF_REG,
|
|
.verr = UNDEF_REG,
|
|
},
|
|
.events = {
|
|
.alra = STM32_RTC_ISR_ALRAF,
|
|
},
|
|
.clear_events = stm32_rtc_clear_events,
|
|
};
|
|
|
|
static const struct stm32_rtc_data stm32h7_rtc_data = {
|
|
.has_pclk = true,
|
|
.need_dbp = true,
|
|
.has_wakeirq = false,
|
|
.regs = {
|
|
.tr = 0x00,
|
|
.dr = 0x04,
|
|
.cr = 0x08,
|
|
.isr = 0x0C,
|
|
.prer = 0x10,
|
|
.alrmar = 0x1C,
|
|
.wpr = 0x24,
|
|
.sr = 0x0C, /* set to ISR offset to ease alarm management */
|
|
.scr = UNDEF_REG,
|
|
.verr = UNDEF_REG,
|
|
},
|
|
.events = {
|
|
.alra = STM32_RTC_ISR_ALRAF,
|
|
},
|
|
.clear_events = stm32_rtc_clear_events,
|
|
};
|
|
|
|
static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
|
|
unsigned int flags)
|
|
{
|
|
struct stm32_rtc_registers regs = rtc->data->regs;
|
|
|
|
/* Flags are cleared by writing 1 in RTC_SCR */
|
|
writel_relaxed(flags, rtc->base + regs.scr);
|
|
}
|
|
|
|
static const struct stm32_rtc_data stm32mp1_data = {
|
|
.has_pclk = true,
|
|
.need_dbp = false,
|
|
.has_wakeirq = true,
|
|
.regs = {
|
|
.tr = 0x00,
|
|
.dr = 0x04,
|
|
.cr = 0x18,
|
|
.isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
|
|
.prer = 0x10,
|
|
.alrmar = 0x40,
|
|
.wpr = 0x24,
|
|
.sr = 0x50,
|
|
.scr = 0x5C,
|
|
.verr = 0x3F4,
|
|
},
|
|
.events = {
|
|
.alra = STM32_RTC_SR_ALRA,
|
|
},
|
|
.clear_events = stm32mp1_rtc_clear_events,
|
|
};
|
|
|
|
static const struct of_device_id stm32_rtc_of_match[] = {
|
|
{ .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
|
|
{ .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
|
|
{ .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
|
|
|
|
static int stm32_rtc_init(struct platform_device *pdev,
|
|
struct stm32_rtc *rtc)
|
|
{
|
|
const struct stm32_rtc_registers *regs = &rtc->data->regs;
|
|
unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
|
|
unsigned int rate;
|
|
int ret = 0;
|
|
|
|
rate = clk_get_rate(rtc->rtc_ck);
|
|
|
|
/* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
|
|
pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
|
|
pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
|
|
|
|
for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
|
|
pred_s = (rate / (pred_a + 1)) - 1;
|
|
|
|
if (((pred_s + 1) * (pred_a + 1)) == rate)
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Can't find a 1Hz, so give priority to RTC power consumption
|
|
* by choosing the higher possible value for prediv_a
|
|
*/
|
|
if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) {
|
|
pred_a = pred_a_max;
|
|
pred_s = (rate / (pred_a + 1)) - 1;
|
|
|
|
dev_warn(&pdev->dev, "rtc_ck is %s\n",
|
|
(rate < ((pred_a + 1) * (pred_s + 1))) ?
|
|
"fast" : "slow");
|
|
}
|
|
|
|
stm32_rtc_wpr_unlock(rtc);
|
|
|
|
ret = stm32_rtc_enter_init_mode(rtc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev,
|
|
"Can't enter in init mode. Prescaler config failed.\n");
|
|
goto end;
|
|
}
|
|
|
|
prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
|
|
writel_relaxed(prer, rtc->base + regs->prer);
|
|
prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
|
|
writel_relaxed(prer, rtc->base + regs->prer);
|
|
|
|
/* Force 24h time format */
|
|
cr = readl_relaxed(rtc->base + regs->cr);
|
|
cr &= ~STM32_RTC_CR_FMT;
|
|
writel_relaxed(cr, rtc->base + regs->cr);
|
|
|
|
stm32_rtc_exit_init_mode(rtc);
|
|
|
|
ret = stm32_rtc_wait_sync(rtc);
|
|
end:
|
|
stm32_rtc_wpr_lock(rtc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_rtc_probe(struct platform_device *pdev)
|
|
{
|
|
struct stm32_rtc *rtc;
|
|
const struct stm32_rtc_registers *regs;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
|
|
if (!rtc)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
rtc->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(rtc->base))
|
|
return PTR_ERR(rtc->base);
|
|
|
|
rtc->data = (struct stm32_rtc_data *)
|
|
of_device_get_match_data(&pdev->dev);
|
|
regs = &rtc->data->regs;
|
|
|
|
if (rtc->data->need_dbp) {
|
|
rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
|
"st,syscfg");
|
|
if (IS_ERR(rtc->dbp)) {
|
|
dev_err(&pdev->dev, "no st,syscfg\n");
|
|
return PTR_ERR(rtc->dbp);
|
|
}
|
|
|
|
ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
|
|
1, &rtc->dbp_reg);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "can't read DBP register offset\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
|
|
2, &rtc->dbp_mask);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "can't read DBP register mask\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (!rtc->data->has_pclk) {
|
|
rtc->pclk = NULL;
|
|
rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
|
|
} else {
|
|
rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
|
|
if (IS_ERR(rtc->pclk)) {
|
|
dev_err(&pdev->dev, "no pclk clock");
|
|
return PTR_ERR(rtc->pclk);
|
|
}
|
|
rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
|
|
}
|
|
if (IS_ERR(rtc->rtc_ck)) {
|
|
dev_err(&pdev->dev, "no rtc_ck clock");
|
|
return PTR_ERR(rtc->rtc_ck);
|
|
}
|
|
|
|
if (rtc->data->has_pclk) {
|
|
ret = clk_prepare_enable(rtc->pclk);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(rtc->rtc_ck);
|
|
if (ret)
|
|
goto err;
|
|
|
|
if (rtc->data->need_dbp)
|
|
regmap_update_bits(rtc->dbp, rtc->dbp_reg,
|
|
rtc->dbp_mask, rtc->dbp_mask);
|
|
|
|
/*
|
|
* After a system reset, RTC_ISR.INITS flag can be read to check if
|
|
* the calendar has been initialized or not. INITS flag is reset by a
|
|
* power-on reset (no vbat, no power-supply). It is not reset if
|
|
* rtc_ck parent clock has changed (so RTC prescalers need to be
|
|
* changed). That's why we cannot rely on this flag to know if RTC
|
|
* init has to be done.
|
|
*/
|
|
ret = stm32_rtc_init(pdev, rtc);
|
|
if (ret)
|
|
goto err;
|
|
|
|
rtc->irq_alarm = platform_get_irq(pdev, 0);
|
|
if (rtc->irq_alarm <= 0) {
|
|
dev_err(&pdev->dev, "no alarm irq\n");
|
|
ret = rtc->irq_alarm;
|
|
goto err;
|
|
}
|
|
|
|
ret = device_init_wakeup(&pdev->dev, true);
|
|
if (rtc->data->has_wakeirq) {
|
|
rtc->wakeirq_alarm = platform_get_irq(pdev, 1);
|
|
if (rtc->wakeirq_alarm > 0) {
|
|
ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
|
|
rtc->wakeirq_alarm);
|
|
} else {
|
|
ret = rtc->wakeirq_alarm;
|
|
if (rtc->wakeirq_alarm == -EPROBE_DEFER)
|
|
goto err;
|
|
}
|
|
}
|
|
if (ret)
|
|
dev_warn(&pdev->dev, "alarm can't wake up the system: %d", ret);
|
|
|
|
platform_set_drvdata(pdev, rtc);
|
|
|
|
rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
|
|
&stm32_rtc_ops, THIS_MODULE);
|
|
if (IS_ERR(rtc->rtc_dev)) {
|
|
ret = PTR_ERR(rtc->rtc_dev);
|
|
dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
|
|
ret);
|
|
goto err;
|
|
}
|
|
|
|
/* Handle RTC alarm interrupts */
|
|
ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
|
|
stm32_rtc_alarm_irq, IRQF_ONESHOT,
|
|
pdev->name, rtc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
|
|
rtc->irq_alarm);
|
|
goto err;
|
|
}
|
|
|
|
/*
|
|
* If INITS flag is reset (calendar year field set to 0x00), calendar
|
|
* must be initialized
|
|
*/
|
|
if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
|
|
dev_warn(&pdev->dev, "Date/Time must be initialized\n");
|
|
|
|
if (regs->verr != UNDEF_REG) {
|
|
u32 ver = readl_relaxed(rtc->base + regs->verr);
|
|
|
|
dev_info(&pdev->dev, "registered rev:%d.%d\n",
|
|
(ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
|
|
(ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
|
|
}
|
|
|
|
return 0;
|
|
err:
|
|
if (rtc->data->has_pclk)
|
|
clk_disable_unprepare(rtc->pclk);
|
|
clk_disable_unprepare(rtc->rtc_ck);
|
|
|
|
if (rtc->data->need_dbp)
|
|
regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
|
|
|
|
dev_pm_clear_wake_irq(&pdev->dev);
|
|
device_init_wakeup(&pdev->dev, false);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_rtc_remove(struct platform_device *pdev)
|
|
{
|
|
struct stm32_rtc *rtc = platform_get_drvdata(pdev);
|
|
const struct stm32_rtc_registers *regs = &rtc->data->regs;
|
|
unsigned int cr;
|
|
|
|
/* Disable interrupts */
|
|
stm32_rtc_wpr_unlock(rtc);
|
|
cr = readl_relaxed(rtc->base + regs->cr);
|
|
cr &= ~STM32_RTC_CR_ALRAIE;
|
|
writel_relaxed(cr, rtc->base + regs->cr);
|
|
stm32_rtc_wpr_lock(rtc);
|
|
|
|
clk_disable_unprepare(rtc->rtc_ck);
|
|
if (rtc->data->has_pclk)
|
|
clk_disable_unprepare(rtc->pclk);
|
|
|
|
/* Enable backup domain write protection if needed */
|
|
if (rtc->data->need_dbp)
|
|
regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
|
|
|
|
dev_pm_clear_wake_irq(&pdev->dev);
|
|
device_init_wakeup(&pdev->dev, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int stm32_rtc_suspend(struct device *dev)
|
|
{
|
|
struct stm32_rtc *rtc = dev_get_drvdata(dev);
|
|
|
|
if (rtc->data->has_pclk)
|
|
clk_disable_unprepare(rtc->pclk);
|
|
|
|
if (device_may_wakeup(dev))
|
|
return enable_irq_wake(rtc->irq_alarm);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_rtc_resume(struct device *dev)
|
|
{
|
|
struct stm32_rtc *rtc = dev_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
if (rtc->data->has_pclk) {
|
|
ret = clk_prepare_enable(rtc->pclk);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = stm32_rtc_wait_sync(rtc);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (device_may_wakeup(dev))
|
|
return disable_irq_wake(rtc->irq_alarm);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops,
|
|
stm32_rtc_suspend, stm32_rtc_resume);
|
|
|
|
static struct platform_driver stm32_rtc_driver = {
|
|
.probe = stm32_rtc_probe,
|
|
.remove = stm32_rtc_remove,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.pm = &stm32_rtc_pm_ops,
|
|
.of_match_table = stm32_rtc_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(stm32_rtc_driver);
|
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
|
|
MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
|
|
MODULE_LICENSE("GPL v2");
|