![Linus Torvalds](/assets/img/avatar_default.png)
A couple of late-merged changes that would be useful to get in this merge window: - Driver support for reset of audio complex on Meson platforms. The audio driver went in this merge window, and these changes have been in -next for a while (just not in our tree). - Power management fixes for IOMMU on Rockchip platforms, getting closer to kexec working on them, including Chromebooks. - Another pass updating "arm,psci" -> "psci" for some properties that have snuck in since last time it was done. -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAluBrbAPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx372IQAJayIgII0C/2MO7aUuVQixoIkSdXmfTbjHSZ JJLiK5Kbua4Gvpq3tkSowg35ohUvPlkoKmDDSTSuiUHGNDQQE9ETQzy5dxrP8R/m dpQpgA41oa9U1Uscl10Bjaf4Oe1NoBhpGx8xrlNYEXRliKkBMulMevj1MovUBSk0 SvuWmwekVrEbVj0cDZ4f5Ze3ODWAkbKdUYebjBHHvDEyHO0J8LJT5Hv98ZEQs+mz BJQeapIXk29Tj1D37+5hoaxglDF4NJvxwQ/VxB7BCXAw2p98Y7TSu473HYkMdp1g ricaldmBlqXVG9KN30tmxjJAgUtupfHicVQ4oNcGQfRWFlwxK8dtKrnzOb6tIRyl S/86gGgFF9jjRlVlRxwCohhswXJR2sqYBw8d10YzsozV/jSgKi+60P8wT+yQIv6H BctwzH4+W7QEAVnx3AvYMWPtgUp1rtvaNjSfz/s7ZAKmEBT/rOD34oXJ8tCnjvVX zsm/5dSqVSbROlP7MY1qC2kHFUQyGcLco45BKXPa6VH/eOkIt3f/VZjXdBmf6CoY xFl7bIoHN8LSt9SdaC3pOfA+oEaM90L+SR8KBK+o58fNiFiwarWqqXR2B7Ql/AKJ j6hic30994/MzUoqCp+stVI2dISb5LofmVpmGeF7CVWihyB6efqzh4RTc1GCKHcK bhNcAMMJ =dQaG -----END PGP SIGNATURE----- Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late updates from Olof Johansson: "A couple of late-merged changes that would be useful to get in this merge window: - Driver support for reset of audio complex on Meson platforms. The audio driver went in this merge window, and these changes have been in -next for a while (just not in our tree). - Power management fixes for IOMMU on Rockchip platforms, getting closer to kexec working on them, including Chromebooks. - Another pass updating "arm,psci" -> "psci" for some properties that have snuck in since last time it was done" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: iommu/rockchip: Move irq request past pm_runtime_enable iommu/rockchip: Handle errors returned from PM framework arm64: rockchip: Force CONFIG_PM on Rockchip systems ARM: rockchip: Force CONFIG_PM on Rockchip systems arm64: dts: Fix various entry-method properties to reflect documentation reset: imx7: Fix always writing bits as 0 reset: meson: add meson audio arb driver reset: meson: add dt-bindings for meson-axg audio arb
160 lines
4.8 KiB
C
160 lines
4.8 KiB
C
/*
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* Copyright (c) 2017, Impinj, Inc.
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*
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* i.MX7 System Reset Controller (SRC) driver
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/regmap.h>
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#include <dt-bindings/reset/imx7-reset.h>
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struct imx7_src {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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enum imx7_src_registers {
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SRC_A7RCR0 = 0x0004,
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SRC_M4RCR = 0x000c,
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SRC_ERCR = 0x0014,
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SRC_HSICPHY_RCR = 0x001c,
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SRC_USBOPHY1_RCR = 0x0020,
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SRC_USBOPHY2_RCR = 0x0024,
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SRC_MIPIPHY_RCR = 0x0028,
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SRC_PCIEPHY_RCR = 0x002c,
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SRC_DDRC_RCR = 0x1000,
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};
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struct imx7_src_signal {
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unsigned int offset, bit;
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};
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static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
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[IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
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[IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
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[IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
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[IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
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[IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
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[IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
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[IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
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[IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
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[IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
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[IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
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[IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
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[IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
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[IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
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[IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
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[IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
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[IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
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[IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
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[IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
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[IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
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[IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
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[IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
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[IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
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[IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
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[IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
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[IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
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};
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static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct imx7_src, rcdev);
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}
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static int imx7_reset_set(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct imx7_src *imx7src = to_imx7_src(rcdev);
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const struct imx7_src_signal *signal = &imx7_src_signals[id];
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unsigned int value = assert ? signal->bit : 0;
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switch (id) {
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case IMX7_RESET_PCIEPHY:
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/*
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* wait for more than 10us to release phy g_rst and
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* btnrst
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*/
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if (!assert)
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udelay(10);
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break;
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case IMX7_RESET_PCIE_CTRL_APPS_EN:
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value = (assert) ? 0 : signal->bit;
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break;
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}
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return regmap_update_bits(imx7src->regmap,
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signal->offset, signal->bit, value);
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}
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static int imx7_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx7_reset_set(rcdev, id, true);
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}
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static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx7_reset_set(rcdev, id, false);
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}
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static const struct reset_control_ops imx7_reset_ops = {
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.assert = imx7_reset_assert,
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.deassert = imx7_reset_deassert,
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};
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static int imx7_reset_probe(struct platform_device *pdev)
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{
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struct imx7_src *imx7src;
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struct device *dev = &pdev->dev;
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struct regmap_config config = { .name = "src" };
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imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
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if (!imx7src)
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return -ENOMEM;
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imx7src->regmap = syscon_node_to_regmap(dev->of_node);
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if (IS_ERR(imx7src->regmap)) {
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dev_err(dev, "Unable to get imx7-src regmap");
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return PTR_ERR(imx7src->regmap);
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}
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regmap_attach_dev(dev, imx7src->regmap, &config);
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imx7src->rcdev.owner = THIS_MODULE;
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imx7src->rcdev.nr_resets = IMX7_RESET_NUM;
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imx7src->rcdev.ops = &imx7_reset_ops;
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imx7src->rcdev.of_node = dev->of_node;
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return devm_reset_controller_register(dev, &imx7src->rcdev);
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}
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static const struct of_device_id imx7_reset_dt_ids[] = {
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{ .compatible = "fsl,imx7d-src", },
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{ /* sentinel */ },
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};
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static struct platform_driver imx7_reset_driver = {
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.probe = imx7_reset_probe,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = imx7_reset_dt_ids,
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},
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};
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builtin_platform_driver(imx7_reset_driver);
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