![Antti Palosaari](/assets/img/avatar_default.png)
Introduce own lock to silence lockdep warning. lockdep validator makes wrong decision when two similar (&map->mutex) locks were taken recursively, even those are different mutexes in a two different drivers. After that patch, functionality remains same, but mutex names are different. That is a temporary hack, proper solution is make regmap aware of locked nested locking rules. ============================================= [ INFO: possible recursive locking detected ] 3.18.0-rc4+ #4 Tainted: G O --------------------------------------------- kdvb-ad-0-fe-0/2814 is trying to acquire lock: (&map->mutex){+.+.+.}, at: [<ffffffff814ec90f>] regmap_lock_mutex+0x2f/0x40 but task is already holding lock: (&map->mutex){+.+.+.}, at: [<ffffffff814ec90f>] regmap_lock_mutex+0x2f/0x40 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&map->mutex); lock(&map->mutex); *** DEADLOCK *** May be due to missing lock nesting notation 1 lock held by kdvb-ad-0-fe-0/2814: #0: (&map->mutex){+.+.+.}, at: [<ffffffff814ec90f>] regmap_lock_mutex+0x2f/0x40 stack backtrace: CPU: 3 PID: 2814 Comm: kdvb-ad-0-fe-0 Tainted: G O 3.18.0-rc4+ #4 Hardware name: System manufacturer System Product Name/M5A78L-M/USB3, BIOS 2001 09/11/2014 0000000000000000 00000000410c8772 ffff880293af3868 ffffffff817a6f82 0000000000000000 ffff8800b3462be0 ffff880293af3968 ffffffff810e7f94 ffff880293af3888 00000000410c8772 ffffffff82dfee60 ffffffff81ab8f89 Call Trace: [<ffffffff817a6f82>] dump_stack+0x4e/0x68 [<ffffffff810e7f94>] __lock_acquire+0x1ea4/0x1f50 [<ffffffff810e2a7d>] ? trace_hardirqs_off+0xd/0x10 [<ffffffff817b01f3>] ? _raw_spin_lock_irqsave+0x83/0xa0 [<ffffffff810e13e6>] ? up+0x16/0x50 [<ffffffff810e2a7d>] ? trace_hardirqs_off+0xd/0x10 [<ffffffff817af8bf>] ? _raw_spin_unlock_irqrestore+0x5f/0x70 [<ffffffff810e9069>] lock_acquire+0xc9/0x170 [<ffffffff814ec90f>] ? regmap_lock_mutex+0x2f/0x40 [<ffffffff817ab50e>] mutex_lock_nested+0x7e/0x430 [<ffffffff814ec90f>] ? regmap_lock_mutex+0x2f/0x40 [<ffffffff814ec90f>] ? regmap_lock_mutex+0x2f/0x40 [<ffffffff817a530b>] ? printk+0x70/0x86 [<ffffffff8110d9e8>] ? mod_timer+0x168/0x240 [<ffffffff814ec90f>] regmap_lock_mutex+0x2f/0x40 [<ffffffff814f08d9>] regmap_update_bits+0x29/0x60 [<ffffffffa03e9778>] rtl2832_select+0x38/0x70 [rtl2832] [<ffffffffa039b03d>] i2c_mux_master_xfer+0x3d/0x90 [i2c_mux] [<ffffffff815da493>] __i2c_transfer+0x73/0x2e0 [<ffffffff815dbaba>] i2c_transfer+0x5a/0xc0 [<ffffffff815dbb6e>] i2c_master_send+0x4e/0x70 [<ffffffffa03ff25a>] regmap_i2c_write+0x1a/0x50 [regmap_i2c] [<ffffffff817ab713>] ? mutex_lock_nested+0x283/0x430 [<ffffffff814f06b2>] _regmap_raw_write+0x862/0x880 [<ffffffff814ec90f>] ? regmap_lock_mutex+0x2f/0x40 [<ffffffff814f0744>] _regmap_bus_raw_write+0x74/0xa0 [<ffffffff814ef3d2>] _regmap_write+0x92/0x140 [<ffffffff814f0b7b>] regmap_write+0x4b/0x70 [<ffffffffa032b090>] ? dvb_frontend_release+0x110/0x110 [dvb_core] [<ffffffffa05141d4>] e4000_init+0x34/0x210 [e4000] [<ffffffffa032a029>] dvb_frontend_init+0x59/0xc0 [dvb_core] [<ffffffff810bde30>] ? finish_task_switch+0x80/0x180 [<ffffffff810bddf2>] ? finish_task_switch+0x42/0x180 [<ffffffffa032b116>] dvb_frontend_thread+0x86/0x7b0 [dvb_core] [<ffffffff817a9203>] ? __schedule+0x343/0x930 [<ffffffffa032b090>] ? dvb_frontend_release+0x110/0x110 [dvb_core] [<ffffffff810b826b>] kthread+0x10b/0x130 [<ffffffff81020099>] ? sched_clock+0x9/0x10 [<ffffffff810b8160>] ? kthread_create_on_node+0x250/0x250 [<ffffffff817b063c>] ret_from_fork+0x7c/0xb0 [<ffffffff810b8160>] ? kthread_create_on_node+0x250/0x250 Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
381 lines
9.7 KiB
C
381 lines
9.7 KiB
C
/*
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* Realtek RTL2832 DVB-T demodulator driver
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*
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* Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
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* Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef RTL2832_PRIV_H
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#define RTL2832_PRIV_H
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#include <linux/regmap.h>
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#include <linux/math64.h>
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#include <linux/bitops.h>
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#include "dvb_frontend.h"
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#include "dvb_math.h"
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#include "rtl2832.h"
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struct rtl2832_dev {
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struct rtl2832_platform_data *pdata;
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struct i2c_client *client;
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struct mutex regmap_mutex;
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struct regmap_config regmap_config;
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struct regmap *regmap;
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struct i2c_adapter *i2c_adapter_tuner;
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struct dvb_frontend fe;
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struct delayed_work stat_work;
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fe_status_t fe_status;
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u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
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u64 post_bit_error;
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u64 post_bit_count;
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bool sleeping;
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struct delayed_work i2c_gate_work;
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unsigned long filters; /* PID filter */
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};
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struct rtl2832_reg_entry {
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u16 start_address;
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u8 msb;
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u8 lsb;
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};
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struct rtl2832_reg_value {
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int reg;
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u32 value;
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};
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/* Demod register bit names */
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enum DVBT_REG_BIT_NAME {
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DVBT_SOFT_RST,
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DVBT_IIC_REPEAT,
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DVBT_TR_WAIT_MIN_8K,
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DVBT_RSD_BER_FAIL_VAL,
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DVBT_EN_BK_TRK,
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DVBT_REG_PI,
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DVBT_REG_PFREQ_1_0,
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DVBT_PD_DA8,
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DVBT_LOCK_TH,
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DVBT_BER_PASS_SCAL,
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DVBT_CE_FFSM_BYPASS,
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DVBT_ALPHAIIR_N,
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DVBT_ALPHAIIR_DIF,
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DVBT_EN_TRK_SPAN,
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DVBT_LOCK_TH_LEN,
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DVBT_CCI_THRE,
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DVBT_CCI_MON_SCAL,
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DVBT_CCI_M0,
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DVBT_CCI_M1,
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DVBT_CCI_M2,
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DVBT_CCI_M3,
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DVBT_SPEC_INIT_0,
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DVBT_SPEC_INIT_1,
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DVBT_SPEC_INIT_2,
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DVBT_AD_EN_REG,
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DVBT_AD_EN_REG1,
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DVBT_EN_BBIN,
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DVBT_MGD_THD0,
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DVBT_MGD_THD1,
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DVBT_MGD_THD2,
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DVBT_MGD_THD3,
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DVBT_MGD_THD4,
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DVBT_MGD_THD5,
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DVBT_MGD_THD6,
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DVBT_MGD_THD7,
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DVBT_EN_CACQ_NOTCH,
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DVBT_AD_AV_REF,
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DVBT_PIP_ON,
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DVBT_SCALE1_B92,
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DVBT_SCALE1_B93,
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DVBT_SCALE1_BA7,
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DVBT_SCALE1_BA9,
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DVBT_SCALE1_BAA,
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DVBT_SCALE1_BAB,
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DVBT_SCALE1_BAC,
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DVBT_SCALE1_BB0,
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DVBT_SCALE1_BB1,
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DVBT_KB_P1,
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DVBT_KB_P2,
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DVBT_KB_P3,
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DVBT_OPT_ADC_IQ,
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DVBT_AD_AVI,
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DVBT_AD_AVQ,
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DVBT_K1_CR_STEP12,
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DVBT_TRK_KS_P2,
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DVBT_TRK_KS_I2,
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DVBT_TR_THD_SET2,
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DVBT_TRK_KC_P2,
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DVBT_TRK_KC_I2,
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DVBT_CR_THD_SET2,
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DVBT_PSET_IFFREQ,
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DVBT_SPEC_INV,
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DVBT_BW_INDEX,
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DVBT_RSAMP_RATIO,
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DVBT_CFREQ_OFF_RATIO,
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DVBT_FSM_STAGE,
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DVBT_RX_CONSTEL,
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DVBT_RX_HIER,
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DVBT_RX_C_RATE_LP,
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DVBT_RX_C_RATE_HP,
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DVBT_GI_IDX,
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DVBT_FFT_MODE_IDX,
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DVBT_RSD_BER_EST,
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DVBT_CE_EST_EVM,
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DVBT_RF_AGC_VAL,
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DVBT_IF_AGC_VAL,
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DVBT_DAGC_VAL,
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DVBT_SFREQ_OFF,
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DVBT_CFREQ_OFF,
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DVBT_POLAR_RF_AGC,
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DVBT_POLAR_IF_AGC,
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DVBT_AAGC_HOLD,
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DVBT_EN_RF_AGC,
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DVBT_EN_IF_AGC,
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DVBT_IF_AGC_MIN,
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DVBT_IF_AGC_MAX,
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DVBT_RF_AGC_MIN,
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DVBT_RF_AGC_MAX,
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DVBT_IF_AGC_MAN,
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DVBT_IF_AGC_MAN_VAL,
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DVBT_RF_AGC_MAN,
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DVBT_RF_AGC_MAN_VAL,
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DVBT_DAGC_TRG_VAL,
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DVBT_AGC_TARG_VAL,
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DVBT_LOOP_GAIN_3_0,
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DVBT_LOOP_GAIN_4,
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DVBT_VTOP,
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DVBT_KRF,
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DVBT_AGC_TARG_VAL_0,
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DVBT_AGC_TARG_VAL_8_1,
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DVBT_AAGC_LOOP_GAIN,
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DVBT_LOOP_GAIN2_3_0,
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DVBT_LOOP_GAIN2_4,
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DVBT_LOOP_GAIN3,
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DVBT_VTOP1,
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DVBT_VTOP2,
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DVBT_VTOP3,
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DVBT_KRF1,
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DVBT_KRF2,
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DVBT_KRF3,
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DVBT_KRF4,
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DVBT_EN_GI_PGA,
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DVBT_THD_LOCK_UP,
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DVBT_THD_LOCK_DW,
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DVBT_THD_UP1,
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DVBT_THD_DW1,
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DVBT_INTER_CNT_LEN,
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DVBT_GI_PGA_STATE,
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DVBT_EN_AGC_PGA,
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DVBT_CKOUTPAR,
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DVBT_CKOUT_PWR,
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DVBT_SYNC_DUR,
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DVBT_ERR_DUR,
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DVBT_SYNC_LVL,
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DVBT_ERR_LVL,
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DVBT_VAL_LVL,
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DVBT_SERIAL,
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DVBT_SER_LSB,
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DVBT_CDIV_PH0,
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DVBT_CDIV_PH1,
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DVBT_MPEG_IO_OPT_2_2,
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DVBT_MPEG_IO_OPT_1_0,
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DVBT_CKOUTPAR_PIP,
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DVBT_CKOUT_PWR_PIP,
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DVBT_SYNC_LVL_PIP,
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DVBT_ERR_LVL_PIP,
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DVBT_VAL_LVL_PIP,
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DVBT_CKOUTPAR_PID,
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DVBT_CKOUT_PWR_PID,
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DVBT_SYNC_LVL_PID,
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DVBT_ERR_LVL_PID,
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DVBT_VAL_LVL_PID,
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DVBT_SM_PASS,
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DVBT_UPDATE_REG_2,
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DVBT_BTHD_P3,
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DVBT_BTHD_D3,
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DVBT_FUNC4_REG0,
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DVBT_FUNC4_REG1,
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DVBT_FUNC4_REG2,
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DVBT_FUNC4_REG3,
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DVBT_FUNC4_REG4,
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DVBT_FUNC4_REG5,
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DVBT_FUNC4_REG6,
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DVBT_FUNC4_REG7,
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DVBT_FUNC4_REG8,
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DVBT_FUNC4_REG9,
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DVBT_FUNC4_REG10,
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DVBT_FUNC5_REG0,
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DVBT_FUNC5_REG1,
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DVBT_FUNC5_REG2,
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DVBT_FUNC5_REG3,
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DVBT_FUNC5_REG4,
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DVBT_FUNC5_REG5,
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DVBT_FUNC5_REG6,
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DVBT_FUNC5_REG7,
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DVBT_FUNC5_REG8,
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DVBT_FUNC5_REG9,
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DVBT_FUNC5_REG10,
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DVBT_FUNC5_REG11,
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DVBT_FUNC5_REG12,
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DVBT_FUNC5_REG13,
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DVBT_FUNC5_REG14,
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DVBT_FUNC5_REG15,
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DVBT_FUNC5_REG16,
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DVBT_FUNC5_REG17,
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DVBT_FUNC5_REG18,
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DVBT_AD7_SETTING,
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DVBT_RSSI_R,
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DVBT_ACI_DET_IND,
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DVBT_REG_MON,
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DVBT_REG_MONSEL,
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DVBT_REG_GPE,
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DVBT_REG_GPO,
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DVBT_REG_4MSEL,
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DVBT_TEST_REG_1,
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DVBT_TEST_REG_2,
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DVBT_TEST_REG_3,
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DVBT_TEST_REG_4,
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DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
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};
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static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
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{DVBT_DAGC_TRG_VAL, 0x39},
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{DVBT_AGC_TARG_VAL_0, 0x0},
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{DVBT_AGC_TARG_VAL_8_1, 0x5a},
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{DVBT_AAGC_LOOP_GAIN, 0x16},
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{DVBT_LOOP_GAIN2_3_0, 0x6},
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{DVBT_LOOP_GAIN2_4, 0x1},
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{DVBT_LOOP_GAIN3, 0x16},
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{DVBT_VTOP1, 0x35},
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{DVBT_VTOP2, 0x21},
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{DVBT_VTOP3, 0x21},
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{DVBT_KRF1, 0x0},
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{DVBT_KRF2, 0x40},
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{DVBT_KRF3, 0x10},
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{DVBT_KRF4, 0x10},
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{DVBT_IF_AGC_MIN, 0x80},
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{DVBT_IF_AGC_MAX, 0x7f},
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{DVBT_RF_AGC_MIN, 0x9c},
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{DVBT_RF_AGC_MAX, 0x7f},
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{DVBT_POLAR_RF_AGC, 0x0},
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{DVBT_POLAR_IF_AGC, 0x0},
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{DVBT_AD7_SETTING, 0xe9f4},
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{DVBT_OPT_ADC_IQ, 0x1},
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{DVBT_AD_AVI, 0x0},
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{DVBT_AD_AVQ, 0x0},
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{DVBT_SPEC_INV, 0x0},
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};
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static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
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{DVBT_DAGC_TRG_VAL, 0x5a},
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{DVBT_AGC_TARG_VAL_0, 0x0},
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{DVBT_AGC_TARG_VAL_8_1, 0x5a},
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{DVBT_AAGC_LOOP_GAIN, 0x16},
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{DVBT_LOOP_GAIN2_3_0, 0x6},
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{DVBT_LOOP_GAIN2_4, 0x1},
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{DVBT_LOOP_GAIN3, 0x16},
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{DVBT_VTOP1, 0x35},
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{DVBT_VTOP2, 0x21},
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{DVBT_VTOP3, 0x21},
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{DVBT_KRF1, 0x0},
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{DVBT_KRF2, 0x40},
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{DVBT_KRF3, 0x10},
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{DVBT_KRF4, 0x10},
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{DVBT_IF_AGC_MIN, 0x80},
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{DVBT_IF_AGC_MAX, 0x7f},
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{DVBT_RF_AGC_MIN, 0x80},
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{DVBT_RF_AGC_MAX, 0x7f},
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{DVBT_POLAR_RF_AGC, 0x0},
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{DVBT_POLAR_IF_AGC, 0x0},
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{DVBT_AD7_SETTING, 0xe9bf},
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{DVBT_EN_GI_PGA, 0x0},
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{DVBT_THD_LOCK_UP, 0x0},
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{DVBT_THD_LOCK_DW, 0x0},
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{DVBT_THD_UP1, 0x11},
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{DVBT_THD_DW1, 0xef},
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{DVBT_INTER_CNT_LEN, 0xc},
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{DVBT_GI_PGA_STATE, 0x0},
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{DVBT_EN_AGC_PGA, 0x1},
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{DVBT_IF_AGC_MAN, 0x0},
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{DVBT_SPEC_INV, 0x0},
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};
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static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
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{DVBT_DAGC_TRG_VAL, 0x5a},
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{DVBT_AGC_TARG_VAL_0, 0x0},
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{DVBT_AGC_TARG_VAL_8_1, 0x5a},
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{DVBT_AAGC_LOOP_GAIN, 0x18},
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{DVBT_LOOP_GAIN2_3_0, 0x8},
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{DVBT_LOOP_GAIN2_4, 0x1},
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{DVBT_LOOP_GAIN3, 0x18},
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{DVBT_VTOP1, 0x35},
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{DVBT_VTOP2, 0x21},
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{DVBT_VTOP3, 0x21},
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{DVBT_KRF1, 0x0},
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{DVBT_KRF2, 0x40},
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{DVBT_KRF3, 0x10},
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{DVBT_KRF4, 0x10},
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{DVBT_IF_AGC_MIN, 0x80},
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{DVBT_IF_AGC_MAX, 0x7f},
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{DVBT_RF_AGC_MIN, 0x80},
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{DVBT_RF_AGC_MAX, 0x7f},
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{DVBT_POLAR_RF_AGC, 0x0},
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{DVBT_POLAR_IF_AGC, 0x0},
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{DVBT_AD7_SETTING, 0xe9d4},
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{DVBT_EN_GI_PGA, 0x0},
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{DVBT_THD_LOCK_UP, 0x0},
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{DVBT_THD_LOCK_DW, 0x0},
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{DVBT_THD_UP1, 0x14},
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{DVBT_THD_DW1, 0xec},
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{DVBT_INTER_CNT_LEN, 0xc},
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{DVBT_GI_PGA_STATE, 0x0},
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{DVBT_EN_AGC_PGA, 0x1},
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{DVBT_REG_GPE, 0x1},
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{DVBT_REG_GPO, 0x1},
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{DVBT_REG_MONSEL, 0x1},
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{DVBT_REG_MON, 0x1},
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{DVBT_REG_4MSEL, 0x0},
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{DVBT_SPEC_INV, 0x0},
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};
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static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
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{DVBT_DAGC_TRG_VAL, 0x39},
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{DVBT_AGC_TARG_VAL_0, 0x0},
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{DVBT_AGC_TARG_VAL_8_1, 0x40},
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{DVBT_AAGC_LOOP_GAIN, 0x16},
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{DVBT_LOOP_GAIN2_3_0, 0x8},
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{DVBT_LOOP_GAIN2_4, 0x1},
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|
{DVBT_LOOP_GAIN3, 0x18},
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{DVBT_VTOP1, 0x35},
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{DVBT_VTOP2, 0x21},
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{DVBT_VTOP3, 0x21},
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|
{DVBT_KRF1, 0x0},
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{DVBT_KRF2, 0x40},
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{DVBT_KRF3, 0x10},
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|
{DVBT_KRF4, 0x10},
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|
{DVBT_IF_AGC_MIN, 0x80},
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|
{DVBT_IF_AGC_MAX, 0x7f},
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|
{DVBT_RF_AGC_MIN, 0x80},
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|
{DVBT_RF_AGC_MAX, 0x7f},
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{DVBT_POLAR_RF_AGC, 0x0},
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|
{DVBT_POLAR_IF_AGC, 0x0},
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{DVBT_AD7_SETTING, 0xe9f4},
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{DVBT_SPEC_INV, 0x1},
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|
};
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#endif /* RTL2832_PRIV_H */
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