![Uwe Kleine-König](/assets/img/avatar_default.png)
The MR25 family doesn't support JEDEC, so they need explicit mentioning in the list of supported spi IDs. This makes it possible to add these using for example: compatible = "everspin,mr25h40"; There was already an entry for mr25h256. Move that one out of the "keep for compatibility" section and put in a new group for Everspin MRAMs. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
347 lines
8.8 KiB
C
347 lines
8.8 KiB
C
/*
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* MTD SPI driver for ST M25Pxx (and similar) serial flash chips
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*
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* Author: Mike Lavender, mike@steroidmicros.com
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*
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* Copyright (c) 2005, Intec Automation Inc.
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*
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* Some parts are based on lart.c by Abraham Van Der Merwe
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*
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* Cleaned up and generalized based on mtd_dataflash.c
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/spi-nor.h>
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#define MAX_CMD_SIZE 6
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struct m25p {
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struct spi_device *spi;
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struct spi_nor spi_nor;
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u8 command[MAX_CMD_SIZE];
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};
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static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
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{
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struct m25p *flash = nor->priv;
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struct spi_device *spi = flash->spi;
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int ret;
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ret = spi_write_then_read(spi, &code, 1, val, len);
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if (ret < 0)
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dev_err(&spi->dev, "error %d reading %x\n", ret, code);
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return ret;
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}
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static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)
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{
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/* opcode is in cmd[0] */
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cmd[1] = addr >> (nor->addr_width * 8 - 8);
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cmd[2] = addr >> (nor->addr_width * 8 - 16);
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cmd[3] = addr >> (nor->addr_width * 8 - 24);
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cmd[4] = addr >> (nor->addr_width * 8 - 32);
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}
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static int m25p_cmdsz(struct spi_nor *nor)
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{
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return 1 + nor->addr_width;
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}
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static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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struct m25p *flash = nor->priv;
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struct spi_device *spi = flash->spi;
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flash->command[0] = opcode;
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if (buf)
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memcpy(&flash->command[1], buf, len);
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return spi_write(spi, flash->command, len + 1);
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}
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static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
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const u_char *buf)
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{
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struct m25p *flash = nor->priv;
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struct spi_device *spi = flash->spi;
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struct spi_transfer t[2] = {};
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struct spi_message m;
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int cmd_sz = m25p_cmdsz(nor);
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ssize_t ret;
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spi_message_init(&m);
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if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
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cmd_sz = 1;
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flash->command[0] = nor->program_opcode;
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m25p_addr2cmd(nor, to, flash->command);
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t[0].tx_buf = flash->command;
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t[0].len = cmd_sz;
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spi_message_add_tail(&t[0], &m);
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t[1].tx_buf = buf;
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t[1].len = len;
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spi_message_add_tail(&t[1], &m);
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ret = spi_sync(spi, &m);
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if (ret)
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return ret;
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ret = m.actual_length - cmd_sz;
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if (ret < 0)
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return -EIO;
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return ret;
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}
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static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
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{
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switch (nor->flash_read) {
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case SPI_NOR_DUAL:
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return 2;
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case SPI_NOR_QUAD:
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return 4;
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default:
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return 0;
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}
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}
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/*
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* Read an address range from the nor chip. The address range
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* may be any size provided it is within the physical boundaries.
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*/
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static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
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u_char *buf)
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{
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struct m25p *flash = nor->priv;
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struct spi_device *spi = flash->spi;
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struct spi_transfer t[2];
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struct spi_message m;
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unsigned int dummy = nor->read_dummy;
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ssize_t ret;
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/* convert the dummy cycles to the number of bytes */
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dummy /= 8;
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if (spi_flash_read_supported(spi)) {
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struct spi_flash_read_message msg;
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memset(&msg, 0, sizeof(msg));
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msg.buf = buf;
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msg.from = from;
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msg.len = len;
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msg.read_opcode = nor->read_opcode;
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msg.addr_width = nor->addr_width;
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msg.dummy_bytes = dummy;
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/* TODO: Support other combinations */
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msg.opcode_nbits = SPI_NBITS_SINGLE;
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msg.addr_nbits = SPI_NBITS_SINGLE;
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msg.data_nbits = m25p80_rx_nbits(nor);
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ret = spi_flash_read(spi, &msg);
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if (ret < 0)
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return ret;
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return msg.retlen;
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}
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spi_message_init(&m);
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memset(t, 0, (sizeof t));
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flash->command[0] = nor->read_opcode;
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m25p_addr2cmd(nor, from, flash->command);
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t[0].tx_buf = flash->command;
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t[0].len = m25p_cmdsz(nor) + dummy;
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].rx_nbits = m25p80_rx_nbits(nor);
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t[1].len = min3(len, spi_max_transfer_size(spi),
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spi_max_message_size(spi) - t[0].len);
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spi_message_add_tail(&t[1], &m);
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ret = spi_sync(spi, &m);
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if (ret)
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return ret;
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ret = m.actual_length - m25p_cmdsz(nor) - dummy;
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if (ret < 0)
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return -EIO;
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return ret;
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}
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/*
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* board specific setup should have ensured the SPI clock used here
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* matches what the READ command supports, at least until this driver
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* understands FAST_READ (for clocks over 25 MHz).
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*/
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static int m25p_probe(struct spi_device *spi)
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{
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struct flash_platform_data *data;
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struct m25p *flash;
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struct spi_nor *nor;
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enum read_mode mode = SPI_NOR_NORMAL;
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char *flash_name;
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int ret;
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data = dev_get_platdata(&spi->dev);
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flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
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if (!flash)
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return -ENOMEM;
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nor = &flash->spi_nor;
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/* install the hooks */
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nor->read = m25p80_read;
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nor->write = m25p80_write;
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nor->write_reg = m25p80_write_reg;
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nor->read_reg = m25p80_read_reg;
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nor->dev = &spi->dev;
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spi_nor_set_flash_node(nor, spi->dev.of_node);
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nor->priv = flash;
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spi_set_drvdata(spi, flash);
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flash->spi = spi;
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if (spi->mode & SPI_RX_QUAD)
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mode = SPI_NOR_QUAD;
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else if (spi->mode & SPI_RX_DUAL)
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mode = SPI_NOR_DUAL;
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if (data && data->name)
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nor->mtd.name = data->name;
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/* For some (historical?) reason many platforms provide two different
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* names in flash_platform_data: "name" and "type". Quite often name is
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* set to "m25p80" and then "type" provides a real chip name.
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* If that's the case, respect "type" and ignore a "name".
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*/
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if (data && data->type)
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flash_name = data->type;
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else if (!strcmp(spi->modalias, "spi-nor"))
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flash_name = NULL; /* auto-detect */
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else
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flash_name = spi->modalias;
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ret = spi_nor_scan(nor, flash_name, mode);
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if (ret)
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return ret;
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return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
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data ? data->nr_parts : 0);
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}
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static int m25p_remove(struct spi_device *spi)
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{
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struct m25p *flash = spi_get_drvdata(spi);
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/* Clean up MTD stuff. */
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return mtd_device_unregister(&flash->spi_nor.mtd);
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}
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/*
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* Do NOT add to this array without reading the following:
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*
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* Historically, many flash devices are bound to this driver by their name. But
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* since most of these flash are compatible to some extent, and their
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* differences can often be differentiated by the JEDEC read-ID command, we
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* encourage new users to add support to the spi-nor library, and simply bind
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* against a generic string here (e.g., "jedec,spi-nor").
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*
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* Many flash names are kept here in this list (as well as in spi-nor.c) to
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* keep them available as module aliases for existing platforms.
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*/
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static const struct spi_device_id m25p_ids[] = {
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/*
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* Allow non-DT platform devices to bind to the "spi-nor" modalias, and
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* hack around the fact that the SPI core does not provide uevent
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* matching for .of_match_table
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*/
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{"spi-nor"},
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/*
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* Entries not used in DTs that should be safe to drop after replacing
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* them with "spi-nor" in platform data.
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*/
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{"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
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/*
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* Entries that were used in DTs without "jedec,spi-nor" fallback and
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* should be kept for backward compatibility.
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*/
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{"at25df321a"}, {"at25df641"}, {"at26df081a"},
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{"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
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{"mx25l25635e"},{"mx66l51235l"},
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{"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
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{"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
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{"s25fl064k"},
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{"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
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{"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
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{"m25p64"}, {"m25p128"},
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{"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
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{"w25q80bl"}, {"w25q128"}, {"w25q256"},
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/* Flashes that can't be detected using JEDEC */
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{"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
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{"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
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{"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
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/* Everspin MRAMs (non-JEDEC) */
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{ "mr25h256" }, /* 256 Kib, 40 MHz */
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{ "mr25h10" }, /* 1 Mib, 40 MHz */
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{ "mr25h40" }, /* 4 Mib, 40 MHz */
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{ },
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};
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MODULE_DEVICE_TABLE(spi, m25p_ids);
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static const struct of_device_id m25p_of_table[] = {
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/*
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* Generic compatibility for SPI NOR that can be identified by the
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* JEDEC READ ID opcode (0x9F). Use this, if possible.
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*/
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{ .compatible = "jedec,spi-nor" },
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{}
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};
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MODULE_DEVICE_TABLE(of, m25p_of_table);
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static struct spi_driver m25p80_driver = {
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.driver = {
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.name = "m25p80",
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.of_match_table = m25p_of_table,
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},
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.id_table = m25p_ids,
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.probe = m25p_probe,
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.remove = m25p_remove,
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/* REVISIT: many of these chips have deep power-down modes, which
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* should clearly be entered on suspend() to minimize power use.
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* And also when they're otherwise idle...
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*/
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};
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module_spi_driver(m25p80_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Mike Lavender");
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MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
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