![Nicholas Mc Guire](/assets/img/avatar_default.png)
This fixes a sparse warning about incorrect type in return expression. Signed-off-by: Nicholas Mc Guire <der.herr@hofr.at> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
778 lines
19 KiB
C
778 lines
19 KiB
C
/*
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* Intel PCH/PCU SPI flash driver.
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*
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* Copyright (C) 2016, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/sizes.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/spi-nor.h>
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#include <linux/platform_data/intel-spi.h>
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#include "intel-spi.h"
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/* Offsets are from @ispi->base */
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#define BFPREG 0x00
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#define HSFSTS_CTL 0x04
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#define HSFSTS_CTL_FSMIE BIT(31)
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#define HSFSTS_CTL_FDBC_SHIFT 24
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#define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
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#define HSFSTS_CTL_FCYCLE_SHIFT 17
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#define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
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/* HW sequencer opcodes */
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#define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
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#define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
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#define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
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#define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
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#define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
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#define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
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#define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
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#define HSFSTS_CTL_FGO BIT(16)
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#define HSFSTS_CTL_FLOCKDN BIT(15)
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#define HSFSTS_CTL_FDV BIT(14)
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#define HSFSTS_CTL_SCIP BIT(5)
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#define HSFSTS_CTL_AEL BIT(2)
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#define HSFSTS_CTL_FCERR BIT(1)
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#define HSFSTS_CTL_FDONE BIT(0)
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#define FADDR 0x08
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#define DLOCK 0x0c
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#define FDATA(n) (0x10 + ((n) * 4))
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#define FRACC 0x50
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#define FREG(n) (0x54 + ((n) * 4))
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#define FREG_BASE_MASK 0x3fff
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#define FREG_LIMIT_SHIFT 16
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#define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
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/* Offset is from @ispi->pregs */
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#define PR(n) ((n) * 4)
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#define PR_WPE BIT(31)
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#define PR_LIMIT_SHIFT 16
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#define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
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#define PR_RPE BIT(15)
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#define PR_BASE_MASK 0x3fff
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/* Last PR is GPR0 */
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#define PR_NUM (5 + 1)
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/* Offsets are from @ispi->sregs */
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#define SSFSTS_CTL 0x00
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#define SSFSTS_CTL_FSMIE BIT(23)
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#define SSFSTS_CTL_DS BIT(22)
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#define SSFSTS_CTL_DBC_SHIFT 16
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#define SSFSTS_CTL_SPOP BIT(11)
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#define SSFSTS_CTL_ACS BIT(10)
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#define SSFSTS_CTL_SCGO BIT(9)
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#define SSFSTS_CTL_COP_SHIFT 12
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#define SSFSTS_CTL_FRS BIT(7)
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#define SSFSTS_CTL_DOFRS BIT(6)
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#define SSFSTS_CTL_AEL BIT(4)
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#define SSFSTS_CTL_FCERR BIT(3)
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#define SSFSTS_CTL_FDONE BIT(2)
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#define SSFSTS_CTL_SCIP BIT(0)
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#define PREOP_OPTYPE 0x04
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#define OPMENU0 0x08
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#define OPMENU1 0x0c
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/* CPU specifics */
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#define BYT_PR 0x74
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#define BYT_SSFSTS_CTL 0x90
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#define BYT_BCR 0xfc
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#define BYT_BCR_WPD BIT(0)
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#define BYT_FREG_NUM 5
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#define LPT_PR 0x74
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#define LPT_SSFSTS_CTL 0x90
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#define LPT_FREG_NUM 5
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#define BXT_PR 0x84
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#define BXT_SSFSTS_CTL 0xa0
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#define BXT_FREG_NUM 12
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#define INTEL_SPI_TIMEOUT 5000 /* ms */
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#define INTEL_SPI_FIFO_SZ 64
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/**
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* struct intel_spi - Driver private data
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* @dev: Device pointer
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* @info: Pointer to board specific info
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* @nor: SPI NOR layer structure
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* @base: Beginning of MMIO space
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* @pregs: Start of protection registers
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* @sregs: Start of software sequencer registers
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* @nregions: Maximum number of regions
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* @writeable: Is the chip writeable
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* @swseq: Use SW sequencer in register reads/writes
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* @erase_64k: 64k erase supported
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* @opcodes: Opcodes which are supported. This are programmed by BIOS
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* before it locks down the controller.
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* @preopcodes: Preopcodes which are supported.
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*/
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struct intel_spi {
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struct device *dev;
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const struct intel_spi_boardinfo *info;
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struct spi_nor nor;
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void __iomem *base;
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void __iomem *pregs;
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void __iomem *sregs;
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size_t nregions;
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bool writeable;
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bool swseq;
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bool erase_64k;
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u8 opcodes[8];
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u8 preopcodes[2];
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};
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static bool writeable;
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module_param(writeable, bool, 0);
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MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
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static void intel_spi_dump_regs(struct intel_spi *ispi)
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{
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u32 value;
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int i;
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dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
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value = readl(ispi->base + HSFSTS_CTL);
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dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
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if (value & HSFSTS_CTL_FLOCKDN)
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dev_dbg(ispi->dev, "-> Locked\n");
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dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
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dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
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for (i = 0; i < 16; i++)
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dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
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i, readl(ispi->base + FDATA(i)));
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dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
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for (i = 0; i < ispi->nregions; i++)
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dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
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readl(ispi->base + FREG(i)));
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for (i = 0; i < PR_NUM; i++)
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dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
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readl(ispi->pregs + PR(i)));
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value = readl(ispi->sregs + SSFSTS_CTL);
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dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
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dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
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readl(ispi->sregs + PREOP_OPTYPE));
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dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0));
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dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1));
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if (ispi->info->type == INTEL_SPI_BYT)
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dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
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dev_dbg(ispi->dev, "Protected regions:\n");
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for (i = 0; i < PR_NUM; i++) {
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u32 base, limit;
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value = readl(ispi->pregs + PR(i));
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if (!(value & (PR_WPE | PR_RPE)))
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continue;
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limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
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base = value & PR_BASE_MASK;
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dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
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i, base << 12, (limit << 12) | 0xfff,
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value & PR_WPE ? 'W' : '.',
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value & PR_RPE ? 'R' : '.');
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}
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dev_dbg(ispi->dev, "Flash regions:\n");
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for (i = 0; i < ispi->nregions; i++) {
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u32 region, base, limit;
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region = readl(ispi->base + FREG(i));
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base = region & FREG_BASE_MASK;
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limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
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if (base >= limit || (i > 0 && limit == 0))
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dev_dbg(ispi->dev, " %02d disabled\n", i);
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else
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dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
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i, base << 12, (limit << 12) | 0xfff);
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}
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dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
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ispi->swseq ? 'S' : 'H');
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}
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/* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
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static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
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{
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size_t bytes;
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int i = 0;
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if (size > INTEL_SPI_FIFO_SZ)
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return -EINVAL;
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while (size > 0) {
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bytes = min_t(size_t, size, 4);
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memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
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size -= bytes;
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buf += bytes;
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i++;
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}
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return 0;
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}
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/* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
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static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
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size_t size)
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{
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size_t bytes;
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int i = 0;
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if (size > INTEL_SPI_FIFO_SZ)
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return -EINVAL;
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while (size > 0) {
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bytes = min_t(size_t, size, 4);
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memcpy_toio(ispi->base + FDATA(i), buf, bytes);
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size -= bytes;
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buf += bytes;
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i++;
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}
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return 0;
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}
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static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
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{
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u32 val;
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return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
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!(val & HSFSTS_CTL_SCIP), 0,
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INTEL_SPI_TIMEOUT * 1000);
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}
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static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
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{
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u32 val;
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return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
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!(val & SSFSTS_CTL_SCIP), 0,
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INTEL_SPI_TIMEOUT * 1000);
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}
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static int intel_spi_init(struct intel_spi *ispi)
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{
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u32 opmenu0, opmenu1, val;
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int i;
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switch (ispi->info->type) {
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case INTEL_SPI_BYT:
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ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
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ispi->pregs = ispi->base + BYT_PR;
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ispi->nregions = BYT_FREG_NUM;
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if (writeable) {
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/* Disable write protection */
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val = readl(ispi->base + BYT_BCR);
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if (!(val & BYT_BCR_WPD)) {
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val |= BYT_BCR_WPD;
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writel(val, ispi->base + BYT_BCR);
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val = readl(ispi->base + BYT_BCR);
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}
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ispi->writeable = !!(val & BYT_BCR_WPD);
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}
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break;
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case INTEL_SPI_LPT:
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ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
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ispi->pregs = ispi->base + LPT_PR;
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ispi->nregions = LPT_FREG_NUM;
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break;
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case INTEL_SPI_BXT:
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ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
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ispi->pregs = ispi->base + BXT_PR;
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ispi->nregions = BXT_FREG_NUM;
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ispi->erase_64k = true;
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break;
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default:
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return -EINVAL;
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}
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/* Disable #SMI generation */
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val = readl(ispi->base + HSFSTS_CTL);
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val &= ~HSFSTS_CTL_FSMIE;
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writel(val, ispi->base + HSFSTS_CTL);
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/*
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* BIOS programs allowed opcodes and then locks down the register.
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* So read back what opcodes it decided to support. That's the set
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* we are going to support as well.
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*/
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opmenu0 = readl(ispi->sregs + OPMENU0);
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opmenu1 = readl(ispi->sregs + OPMENU1);
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/*
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* Some controllers can only do basic operations using hardware
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* sequencer. All other operations are supposed to be carried out
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* using software sequencer. If we find that BIOS has programmed
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* opcodes for the software sequencer we use that over the hardware
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* sequencer.
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*/
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if (opmenu0 && opmenu1) {
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for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
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ispi->opcodes[i] = opmenu0 >> i * 8;
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ispi->opcodes[i + 4] = opmenu1 >> i * 8;
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}
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val = readl(ispi->sregs + PREOP_OPTYPE);
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ispi->preopcodes[0] = val;
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ispi->preopcodes[1] = val >> 8;
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/* Disable #SMI generation from SW sequencer */
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val = readl(ispi->sregs + SSFSTS_CTL);
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val &= ~SSFSTS_CTL_FSMIE;
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writel(val, ispi->sregs + SSFSTS_CTL);
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ispi->swseq = true;
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}
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intel_spi_dump_regs(ispi);
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return 0;
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}
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static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
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if (ispi->opcodes[i] == opcode)
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return i;
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return -EINVAL;
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}
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static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, u8 *buf,
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int len)
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{
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u32 val, status;
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int ret;
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val = readl(ispi->base + HSFSTS_CTL);
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val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
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switch (opcode) {
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case SPINOR_OP_RDID:
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val |= HSFSTS_CTL_FCYCLE_RDID;
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break;
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case SPINOR_OP_WRSR:
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val |= HSFSTS_CTL_FCYCLE_WRSR;
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break;
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case SPINOR_OP_RDSR:
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val |= HSFSTS_CTL_FCYCLE_RDSR;
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break;
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default:
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return -EINVAL;
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}
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val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
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val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
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val |= HSFSTS_CTL_FGO;
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writel(val, ispi->base + HSFSTS_CTL);
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ret = intel_spi_wait_hw_busy(ispi);
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if (ret)
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return ret;
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status = readl(ispi->base + HSFSTS_CTL);
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if (status & HSFSTS_CTL_FCERR)
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return -EIO;
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else if (status & HSFSTS_CTL_AEL)
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return -EACCES;
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return 0;
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}
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static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, u8 *buf,
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int len)
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{
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u32 val, status;
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int ret;
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ret = intel_spi_opcode_index(ispi, opcode);
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if (ret < 0)
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return ret;
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val = (len << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
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val |= ret << SSFSTS_CTL_COP_SHIFT;
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val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
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val |= SSFSTS_CTL_SCGO;
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writel(val, ispi->sregs + SSFSTS_CTL);
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ret = intel_spi_wait_sw_busy(ispi);
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if (ret)
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return ret;
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status = readl(ispi->base + SSFSTS_CTL);
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if (status & SSFSTS_CTL_FCERR)
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return -EIO;
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else if (status & SSFSTS_CTL_AEL)
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return -EACCES;
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return 0;
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}
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static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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struct intel_spi *ispi = nor->priv;
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int ret;
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/* Address of the first chip */
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writel(0, ispi->base + FADDR);
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if (ispi->swseq)
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ret = intel_spi_sw_cycle(ispi, opcode, buf, len);
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else
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ret = intel_spi_hw_cycle(ispi, opcode, buf, len);
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if (ret)
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return ret;
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return intel_spi_read_block(ispi, buf, len);
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}
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static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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struct intel_spi *ispi = nor->priv;
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|
int ret;
|
|
|
|
/*
|
|
* This is handled with atomic operation and preop code in Intel
|
|
* controller so skip it here now.
|
|
*/
|
|
if (opcode == SPINOR_OP_WREN)
|
|
return 0;
|
|
|
|
writel(0, ispi->base + FADDR);
|
|
|
|
/* Write the value beforehand */
|
|
ret = intel_spi_write_block(ispi, buf, len);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (ispi->swseq)
|
|
return intel_spi_sw_cycle(ispi, opcode, buf, len);
|
|
return intel_spi_hw_cycle(ispi, opcode, buf, len);
|
|
}
|
|
|
|
static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
|
|
u_char *read_buf)
|
|
{
|
|
struct intel_spi *ispi = nor->priv;
|
|
size_t block_size, retlen = 0;
|
|
u32 val, status;
|
|
ssize_t ret;
|
|
|
|
switch (nor->read_opcode) {
|
|
case SPINOR_OP_READ:
|
|
case SPINOR_OP_READ_FAST:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
while (len > 0) {
|
|
block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
|
|
|
|
writel(from, ispi->base + FADDR);
|
|
|
|
val = readl(ispi->base + HSFSTS_CTL);
|
|
val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
|
|
val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
|
|
val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
|
|
val |= HSFSTS_CTL_FCYCLE_READ;
|
|
val |= HSFSTS_CTL_FGO;
|
|
writel(val, ispi->base + HSFSTS_CTL);
|
|
|
|
ret = intel_spi_wait_hw_busy(ispi);
|
|
if (ret)
|
|
return ret;
|
|
|
|
status = readl(ispi->base + HSFSTS_CTL);
|
|
if (status & HSFSTS_CTL_FCERR)
|
|
ret = -EIO;
|
|
else if (status & HSFSTS_CTL_AEL)
|
|
ret = -EACCES;
|
|
|
|
if (ret < 0) {
|
|
dev_err(ispi->dev, "read error: %llx: %#x\n", from,
|
|
status);
|
|
return ret;
|
|
}
|
|
|
|
ret = intel_spi_read_block(ispi, read_buf, block_size);
|
|
if (ret)
|
|
return ret;
|
|
|
|
len -= block_size;
|
|
from += block_size;
|
|
retlen += block_size;
|
|
read_buf += block_size;
|
|
}
|
|
|
|
return retlen;
|
|
}
|
|
|
|
static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
|
|
const u_char *write_buf)
|
|
{
|
|
struct intel_spi *ispi = nor->priv;
|
|
size_t block_size, retlen = 0;
|
|
u32 val, status;
|
|
ssize_t ret;
|
|
|
|
while (len > 0) {
|
|
block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
|
|
|
|
writel(to, ispi->base + FADDR);
|
|
|
|
val = readl(ispi->base + HSFSTS_CTL);
|
|
val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
|
|
val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
|
|
val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
|
|
val |= HSFSTS_CTL_FCYCLE_WRITE;
|
|
|
|
/* Write enable */
|
|
if (ispi->preopcodes[1] == SPINOR_OP_WREN)
|
|
val |= SSFSTS_CTL_SPOP;
|
|
val |= SSFSTS_CTL_ACS;
|
|
writel(val, ispi->base + HSFSTS_CTL);
|
|
|
|
ret = intel_spi_write_block(ispi, write_buf, block_size);
|
|
if (ret) {
|
|
dev_err(ispi->dev, "failed to write block\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Start the write now */
|
|
val = readl(ispi->base + HSFSTS_CTL);
|
|
writel(val | HSFSTS_CTL_FGO, ispi->base + HSFSTS_CTL);
|
|
|
|
ret = intel_spi_wait_hw_busy(ispi);
|
|
if (ret) {
|
|
dev_err(ispi->dev, "timeout\n");
|
|
return ret;
|
|
}
|
|
|
|
status = readl(ispi->base + HSFSTS_CTL);
|
|
if (status & HSFSTS_CTL_FCERR)
|
|
ret = -EIO;
|
|
else if (status & HSFSTS_CTL_AEL)
|
|
ret = -EACCES;
|
|
|
|
if (ret < 0) {
|
|
dev_err(ispi->dev, "write error: %llx: %#x\n", to,
|
|
status);
|
|
return ret;
|
|
}
|
|
|
|
len -= block_size;
|
|
to += block_size;
|
|
retlen += block_size;
|
|
write_buf += block_size;
|
|
}
|
|
|
|
return retlen;
|
|
}
|
|
|
|
static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
|
|
{
|
|
size_t erase_size, len = nor->mtd.erasesize;
|
|
struct intel_spi *ispi = nor->priv;
|
|
u32 val, status, cmd;
|
|
int ret;
|
|
|
|
/* If the hardware can do 64k erase use that when possible */
|
|
if (len >= SZ_64K && ispi->erase_64k) {
|
|
cmd = HSFSTS_CTL_FCYCLE_ERASE_64K;
|
|
erase_size = SZ_64K;
|
|
} else {
|
|
cmd = HSFSTS_CTL_FCYCLE_ERASE;
|
|
erase_size = SZ_4K;
|
|
}
|
|
|
|
while (len > 0) {
|
|
writel(offs, ispi->base + FADDR);
|
|
|
|
val = readl(ispi->base + HSFSTS_CTL);
|
|
val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
|
|
val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
|
|
val |= cmd;
|
|
val |= HSFSTS_CTL_FGO;
|
|
writel(val, ispi->base + HSFSTS_CTL);
|
|
|
|
ret = intel_spi_wait_hw_busy(ispi);
|
|
if (ret)
|
|
return ret;
|
|
|
|
status = readl(ispi->base + HSFSTS_CTL);
|
|
if (status & HSFSTS_CTL_FCERR)
|
|
return -EIO;
|
|
else if (status & HSFSTS_CTL_AEL)
|
|
return -EACCES;
|
|
|
|
offs += erase_size;
|
|
len -= erase_size;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool intel_spi_is_protected(const struct intel_spi *ispi,
|
|
unsigned int base, unsigned int limit)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < PR_NUM; i++) {
|
|
u32 pr_base, pr_limit, pr_value;
|
|
|
|
pr_value = readl(ispi->pregs + PR(i));
|
|
if (!(pr_value & (PR_WPE | PR_RPE)))
|
|
continue;
|
|
|
|
pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
|
|
pr_base = pr_value & PR_BASE_MASK;
|
|
|
|
if (pr_base >= base && pr_limit <= limit)
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* There will be a single partition holding all enabled flash regions. We
|
|
* call this "BIOS".
|
|
*/
|
|
static void intel_spi_fill_partition(struct intel_spi *ispi,
|
|
struct mtd_partition *part)
|
|
{
|
|
u64 end;
|
|
int i;
|
|
|
|
memset(part, 0, sizeof(*part));
|
|
|
|
/* Start from the mandatory descriptor region */
|
|
part->size = 4096;
|
|
part->name = "BIOS";
|
|
|
|
/*
|
|
* Now try to find where this partition ends based on the flash
|
|
* region registers.
|
|
*/
|
|
for (i = 1; i < ispi->nregions; i++) {
|
|
u32 region, base, limit;
|
|
|
|
region = readl(ispi->base + FREG(i));
|
|
base = region & FREG_BASE_MASK;
|
|
limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
|
|
|
|
if (base >= limit || limit == 0)
|
|
continue;
|
|
|
|
/*
|
|
* If any of the regions have protection bits set, make the
|
|
* whole partition read-only to be on the safe side.
|
|
*/
|
|
if (intel_spi_is_protected(ispi, base, limit))
|
|
ispi->writeable = false;
|
|
|
|
end = (limit << 12) + 4096;
|
|
if (end > part->size)
|
|
part->size = end;
|
|
}
|
|
}
|
|
|
|
struct intel_spi *intel_spi_probe(struct device *dev,
|
|
struct resource *mem, const struct intel_spi_boardinfo *info)
|
|
{
|
|
struct mtd_partition part;
|
|
struct intel_spi *ispi;
|
|
int ret;
|
|
|
|
if (!info || !mem)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
|
|
if (!ispi)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
ispi->base = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(ispi->base))
|
|
return ERR_CAST(ispi->base);
|
|
|
|
ispi->dev = dev;
|
|
ispi->info = info;
|
|
ispi->writeable = info->writeable;
|
|
|
|
ret = intel_spi_init(ispi);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
|
|
ispi->nor.dev = ispi->dev;
|
|
ispi->nor.priv = ispi;
|
|
ispi->nor.read_reg = intel_spi_read_reg;
|
|
ispi->nor.write_reg = intel_spi_write_reg;
|
|
ispi->nor.read = intel_spi_read;
|
|
ispi->nor.write = intel_spi_write;
|
|
ispi->nor.erase = intel_spi_erase;
|
|
|
|
ret = spi_nor_scan(&ispi->nor, NULL, SPI_NOR_NORMAL);
|
|
if (ret) {
|
|
dev_info(dev, "failed to locate the chip\n");
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
intel_spi_fill_partition(ispi, &part);
|
|
|
|
/* Prevent writes if not explicitly enabled */
|
|
if (!ispi->writeable || !writeable)
|
|
ispi->nor.mtd.flags &= ~MTD_WRITEABLE;
|
|
|
|
ret = mtd_device_parse_register(&ispi->nor.mtd, NULL, NULL, &part, 1);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
|
|
return ispi;
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_spi_probe);
|
|
|
|
int intel_spi_remove(struct intel_spi *ispi)
|
|
{
|
|
return mtd_device_unregister(&ispi->nor.mtd);
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_spi_remove);
|
|
|
|
MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
|
|
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
|
|
MODULE_LICENSE("GPL v2");
|