![Magnus Damm](/assets/img/avatar_default.png)
This patch reworks the mode pin code to keep the pin definitions in one place. The mode pins values are now the value of the bit instead of bit number. With this patch in place the sh7785 header file contains mode pin comments. The sh7785 clock code and the sh7785lcr board code are updated to reflect the new shared mode pins. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
260 lines
5.3 KiB
C
260 lines
5.3 KiB
C
#ifndef __ASM_SH7785_H__
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#define __ASM_SH7785_H__
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/* Boot Mode Pins:
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*
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* MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
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* MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
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* MODE2: CPG - Reserved (L: Normal operation)
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* MODE3: CPG - Reserved (L: Normal operation)
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* MODE4: CPG - Initial PLL setting (72x/36x)
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* MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
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* MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
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* MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
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* MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
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* MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30]
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* MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal)
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* MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave)
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* MODE12: PCI - Pin Mode (HL: Local bus, HH: DU)
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* MODE13: Boot Address Mode (L: 29-bit, H: 32-bit)
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* MODE14: Reserved (H: Normal operation)
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*
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* More information in sh7785 manual Rev.1.00, page 1628.
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*/
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/* Pin Function Controller:
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* GPIO_FN_xx - GPIO used to select pin function
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* GPIO_Pxx - GPIO mapped to real I/O pin on CPU
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*/
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enum {
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/* PA */
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GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
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GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
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/* PB */
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GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
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GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
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/* PC */
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GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
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GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
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/* PD */
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GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
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GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
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/* PE */
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GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
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GPIO_PE1, GPIO_PE0,
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/* PF */
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GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
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GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
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/* PG */
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GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
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GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
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/* PH */
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GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
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GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
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/* PJ */
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GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
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GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
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/* PK */
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GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4,
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GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0,
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/* PL */
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GPIO_PL7, GPIO_PL6, GPIO_PL5, GPIO_PL4,
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GPIO_PL3, GPIO_PL2, GPIO_PL1, GPIO_PL0,
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/* PM */
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GPIO_PM1, GPIO_PM0,
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/* PN */
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GPIO_PN7, GPIO_PN6, GPIO_PN5, GPIO_PN4,
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GPIO_PN3, GPIO_PN2, GPIO_PN1, GPIO_PN0,
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/* PP */
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GPIO_PP5, GPIO_PP4,
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GPIO_PP3, GPIO_PP2, GPIO_PP1, GPIO_PP0,
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/* PQ */
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GPIO_PQ4,
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GPIO_PQ3, GPIO_PQ2, GPIO_PQ1, GPIO_PQ0,
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/* PR */
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GPIO_PR3, GPIO_PR2, GPIO_PR1, GPIO_PR0,
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GPIO_FN_D63_AD31,
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GPIO_FN_D62_AD30,
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GPIO_FN_D61_AD29,
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GPIO_FN_D60_AD28,
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GPIO_FN_D59_AD27,
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GPIO_FN_D58_AD26,
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GPIO_FN_D57_AD25,
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GPIO_FN_D56_AD24,
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GPIO_FN_D55_AD23,
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GPIO_FN_D54_AD22,
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GPIO_FN_D53_AD21,
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GPIO_FN_D52_AD20,
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GPIO_FN_D51_AD19,
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GPIO_FN_D50_AD18,
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GPIO_FN_D49_AD17_DB5,
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GPIO_FN_D48_AD16_DB4,
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GPIO_FN_D47_AD15_DB3,
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GPIO_FN_D46_AD14_DB2,
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GPIO_FN_D45_AD13_DB1,
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GPIO_FN_D44_AD12_DB0,
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GPIO_FN_D43_AD11_DG5,
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GPIO_FN_D42_AD10_DG4,
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GPIO_FN_D41_AD9_DG3,
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GPIO_FN_D40_AD8_DG2,
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GPIO_FN_D39_AD7_DG1,
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GPIO_FN_D38_AD6_DG0,
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GPIO_FN_D37_AD5_DR5,
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GPIO_FN_D36_AD4_DR4,
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GPIO_FN_D35_AD3_DR3,
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GPIO_FN_D34_AD2_DR2,
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GPIO_FN_D33_AD1_DR1,
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GPIO_FN_D32_AD0_DR0,
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GPIO_FN_REQ1,
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GPIO_FN_REQ2,
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GPIO_FN_REQ3,
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GPIO_FN_GNT1,
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GPIO_FN_GNT2,
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GPIO_FN_GNT3,
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GPIO_FN_MMCCLK,
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GPIO_FN_D31,
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GPIO_FN_D30,
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GPIO_FN_D29,
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GPIO_FN_D28,
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GPIO_FN_D27,
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GPIO_FN_D26,
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GPIO_FN_D25,
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GPIO_FN_D24,
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GPIO_FN_D23,
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GPIO_FN_D22,
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GPIO_FN_D21,
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GPIO_FN_D20,
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GPIO_FN_D19,
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GPIO_FN_D18,
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GPIO_FN_D17,
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GPIO_FN_D16,
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GPIO_FN_SCIF1_SCK,
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GPIO_FN_SCIF1_RXD,
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GPIO_FN_SCIF1_TXD,
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GPIO_FN_SCIF0_CTS,
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GPIO_FN_INTD,
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GPIO_FN_FCE,
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GPIO_FN_SCIF0_RTS,
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GPIO_FN_HSPI_CS,
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GPIO_FN_FSE,
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GPIO_FN_SCIF0_SCK,
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GPIO_FN_HSPI_CLK,
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GPIO_FN_FRE,
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GPIO_FN_SCIF0_RXD,
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GPIO_FN_HSPI_RX,
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GPIO_FN_FRB,
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GPIO_FN_SCIF0_TXD,
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GPIO_FN_HSPI_TX,
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GPIO_FN_FWE,
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GPIO_FN_SCIF5_TXD,
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GPIO_FN_HAC1_SYNC,
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GPIO_FN_SSI1_WS,
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GPIO_FN_SIOF_TXD_PJ,
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GPIO_FN_HAC0_SDOUT,
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GPIO_FN_SSI0_SDATA,
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GPIO_FN_SIOF_RXD_PJ,
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GPIO_FN_HAC0_SDIN,
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GPIO_FN_SSI0_SCK,
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GPIO_FN_SIOF_SYNC_PJ,
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GPIO_FN_HAC0_SYNC,
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GPIO_FN_SSI0_WS,
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GPIO_FN_SIOF_MCLK_PJ,
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GPIO_FN_HAC_RES,
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GPIO_FN_SIOF_SCK_PJ,
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GPIO_FN_HAC0_BITCLK,
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GPIO_FN_SSI0_CLK,
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GPIO_FN_HAC1_BITCLK,
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GPIO_FN_SSI1_CLK,
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GPIO_FN_TCLK,
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GPIO_FN_IOIS16,
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GPIO_FN_STATUS0,
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GPIO_FN_DRAK0_PK3,
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GPIO_FN_STATUS1,
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GPIO_FN_DRAK1_PK2,
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GPIO_FN_DACK2,
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GPIO_FN_SCIF2_TXD,
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GPIO_FN_MMCCMD,
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GPIO_FN_SIOF_TXD_PK,
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GPIO_FN_DACK3,
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GPIO_FN_SCIF2_SCK,
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GPIO_FN_MMCDAT,
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GPIO_FN_SIOF_SCK_PK,
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GPIO_FN_DREQ0,
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GPIO_FN_DREQ1,
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GPIO_FN_DRAK0_PK1,
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GPIO_FN_DRAK1_PK0,
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GPIO_FN_DREQ2,
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GPIO_FN_INTB,
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GPIO_FN_DREQ3,
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GPIO_FN_INTC,
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GPIO_FN_DRAK2,
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GPIO_FN_CE2A,
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GPIO_FN_IRL4,
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GPIO_FN_FD4,
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GPIO_FN_IRL5,
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GPIO_FN_FD5,
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GPIO_FN_IRL6,
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GPIO_FN_FD6,
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GPIO_FN_IRL7,
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GPIO_FN_FD7,
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GPIO_FN_DRAK3,
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GPIO_FN_CE2B,
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GPIO_FN_BREQ_BSACK,
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GPIO_FN_BACK_BSREQ,
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GPIO_FN_SCIF5_RXD,
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GPIO_FN_HAC1_SDIN,
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GPIO_FN_SSI1_SCK,
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GPIO_FN_SCIF5_SCK,
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GPIO_FN_HAC1_SDOUT,
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GPIO_FN_SSI1_SDATA,
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GPIO_FN_SCIF3_TXD,
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GPIO_FN_FCLE,
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GPIO_FN_SCIF3_RXD,
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GPIO_FN_FALE,
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GPIO_FN_SCIF3_SCK,
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GPIO_FN_FD0,
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GPIO_FN_SCIF4_TXD,
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GPIO_FN_FD1,
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GPIO_FN_SCIF4_RXD,
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GPIO_FN_FD2,
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GPIO_FN_SCIF4_SCK,
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GPIO_FN_FD3,
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GPIO_FN_DEVSEL_DCLKOUT,
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GPIO_FN_STOP_CDE,
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GPIO_FN_LOCK_ODDF,
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GPIO_FN_TRDY_DISPL,
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GPIO_FN_IRDY_HSYNC,
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GPIO_FN_PCIFRAME_VSYNC,
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GPIO_FN_INTA,
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GPIO_FN_GNT0_GNTIN,
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GPIO_FN_REQ0_REQOUT,
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GPIO_FN_PERR,
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GPIO_FN_SERR,
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GPIO_FN_WE7_CBE3,
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GPIO_FN_WE6_CBE2,
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GPIO_FN_WE5_CBE1,
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GPIO_FN_WE4_CBE0,
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GPIO_FN_SCIF2_RXD,
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GPIO_FN_SIOF_RXD,
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GPIO_FN_MRESETOUT,
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GPIO_FN_IRQOUT,
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};
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#endif /* __ASM_SH7785_H__ */
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