120 lines
2.8 KiB
C
120 lines
2.8 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include "i915_selftest.h"
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#include "gt/intel_gt.h"
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#include "selftests/igt_flush_test.h"
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#include "selftests/mock_drm.h"
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#include "huge_gem_object.h"
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#include "mock_context.h"
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static int igt_client_fill(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_context *ce = i915->engine[BCS0]->kernel_context;
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struct drm_i915_gem_object *obj;
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struct rnd_state prng;
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IGT_TIMEOUT(end);
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u32 *vaddr;
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int err = 0;
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prandom_seed_state(&prng, i915_selftest.random_seed);
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do {
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const u32 max_block_size = S16_MAX * PAGE_SIZE;
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u32 sz = min_t(u64, ce->vm->total >> 4, prandom_u32_state(&prng));
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u32 phys_sz = sz % (max_block_size + 1);
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u32 val = prandom_u32_state(&prng);
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u32 i;
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sz = round_up(sz, PAGE_SIZE);
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phys_sz = round_up(phys_sz, PAGE_SIZE);
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pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__,
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phys_sz, sz, val);
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obj = huge_gem_object(i915, phys_sz, sz);
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if (IS_ERR(obj)) {
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err = PTR_ERR(obj);
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goto err_flush;
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}
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vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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err = PTR_ERR(vaddr);
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goto err_put;
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}
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/*
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* XXX: The goal is move this to get_pages, so try to dirty the
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* CPU cache first to check that we do the required clflush
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* before scheduling the blt for !llc platforms. This matches
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* some version of reality where at get_pages the pages
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* themselves may not yet be coherent with the GPU(swap-in). If
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* we are missing the flush then we should see the stale cache
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* values after we do the set_to_cpu_domain and pick it up as a
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* test failure.
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*/
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memset32(vaddr, val ^ 0xdeadbeaf,
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huge_gem_object_phys_size(obj) / sizeof(u32));
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if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
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obj->cache_dirty = true;
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err = i915_gem_schedule_fill_pages_blt(obj, ce, obj->mm.pages,
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&obj->mm.page_sizes,
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val);
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if (err)
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goto err_unpin;
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i915_gem_object_lock(obj);
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err = i915_gem_object_set_to_cpu_domain(obj, false);
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i915_gem_object_unlock(obj);
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if (err)
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goto err_unpin;
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for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); ++i) {
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if (vaddr[i] != val) {
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pr_err("vaddr[%u]=%x, expected=%x\n", i,
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vaddr[i], val);
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err = -EINVAL;
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goto err_unpin;
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}
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}
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i915_gem_object_unpin_map(obj);
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i915_gem_object_put(obj);
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} while (!time_after(jiffies, end));
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goto err_flush;
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err_unpin:
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i915_gem_object_unpin_map(obj);
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err_put:
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i915_gem_object_put(obj);
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err_flush:
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if (err == -ENOMEM)
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err = 0;
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return err;
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}
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int i915_gem_client_blt_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(igt_client_fill),
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};
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if (intel_gt_is_wedged(&i915->gt))
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return 0;
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if (!HAS_ENGINE(i915, BCS0))
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return 0;
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return i915_live_subtests(tests, i915);
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}
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