![Scott Wood](/assets/img/avatar_default.png)
The only way Freescale booke chips support mappings larger than 4K is via TLB1. The only way we support (direct) TLB1 entries is via hugetlb, which is not what map_kernel_page() does when given a large page size. Without this, a kernel with CONFIG_SPARSEMEM_VMEMMAP enabled crashes on boot with messages such as: PID hash table entries: 4096 (order: 3, 32768 bytes) Sorting __ex_table... BUG: Bad page state in process swapper pfn:00a2f page:8000040000023a48 count:0 mapcount:0 mapping:0000040000ffce48 index:0x40000ffbe50 page flags: 0x40000ffda40(active|arch_1|private|private_2|head|tail|swapcache|mappedtodisk|reclaim|swapbacked|unevictable|mlocked) page dumped because: PAGE_FLAGS_CHECK_AT_FREE flag(s) set bad because of flags: page flags: 0x311840(active|private|private_2|swapcache|unevictable|mlocked) Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 3.15.0-rc1-00003-g7fa250c #299 Call Trace: [c00000000098ba20] [c000000000008b3c] .show_stack+0x7c/0x1cc (unreliable) [c00000000098baf0] [c00000000060aa50] .dump_stack+0x88/0xb4 [c00000000098bb70] [c0000000000c0468] .bad_page+0x144/0x1a0 [c00000000098bc10] [c0000000000c0628] .free_pages_prepare+0x164/0x17c [c00000000098bcc0] [c0000000000c24cc] .free_hot_cold_page+0x48/0x214 [c00000000098bd60] [c00000000086c318] .free_all_bootmem+0x1fc/0x354 [c00000000098be70] [c00000000085da84] .mem_init+0xac/0xdc [c00000000098bef0] [c0000000008547b0] .start_kernel+0x21c/0x4d4 [c00000000098bf90] [c000000000000448] .start_here_common+0x20/0x58 Signed-off-by: Scott Wood <scottwood@freescale.com>
733 lines
18 KiB
C
733 lines
18 KiB
C
/*
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* This file contains the routines for TLB flushing.
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* On machines where the MMU does not use a hash table to store virtual to
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* physical translations (ie, SW loaded TLBs or Book3E compilant processors,
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* this does -not- include 603 however which shares the implementation with
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* hash based processors)
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*
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* -- BenH
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*
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* Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
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* IBM Corp.
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/highmem.h>
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#include <linux/pagemap.h>
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#include <linux/preempt.h>
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#include <linux/spinlock.h>
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#include <linux/memblock.h>
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#include <linux/of_fdt.h>
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#include <linux/hugetlb.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include <asm/code-patching.h>
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#include <asm/hugetlb.h>
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#include <asm/paca.h>
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#include "mmu_decl.h"
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/*
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* This struct lists the sw-supported page sizes. The hardawre MMU may support
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* other sizes not listed here. The .ind field is only used on MMUs that have
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* indirect page table entries.
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*/
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#ifdef CONFIG_PPC_BOOK3E_MMU
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#ifdef CONFIG_PPC_FSL_BOOK3E
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struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
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[MMU_PAGE_4K] = {
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.shift = 12,
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.enc = BOOK3E_PAGESZ_4K,
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},
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[MMU_PAGE_2M] = {
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.shift = 21,
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.enc = BOOK3E_PAGESZ_2M,
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},
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[MMU_PAGE_4M] = {
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.shift = 22,
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.enc = BOOK3E_PAGESZ_4M,
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},
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[MMU_PAGE_16M] = {
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.shift = 24,
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.enc = BOOK3E_PAGESZ_16M,
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},
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[MMU_PAGE_64M] = {
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.shift = 26,
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.enc = BOOK3E_PAGESZ_64M,
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},
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[MMU_PAGE_256M] = {
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.shift = 28,
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.enc = BOOK3E_PAGESZ_256M,
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},
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[MMU_PAGE_1G] = {
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.shift = 30,
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.enc = BOOK3E_PAGESZ_1GB,
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},
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};
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#else
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struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
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[MMU_PAGE_4K] = {
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.shift = 12,
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.ind = 20,
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.enc = BOOK3E_PAGESZ_4K,
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},
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[MMU_PAGE_16K] = {
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.shift = 14,
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.enc = BOOK3E_PAGESZ_16K,
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},
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[MMU_PAGE_64K] = {
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.shift = 16,
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.ind = 28,
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.enc = BOOK3E_PAGESZ_64K,
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},
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[MMU_PAGE_1M] = {
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.shift = 20,
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.enc = BOOK3E_PAGESZ_1M,
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},
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[MMU_PAGE_16M] = {
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.shift = 24,
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.ind = 36,
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.enc = BOOK3E_PAGESZ_16M,
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},
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[MMU_PAGE_256M] = {
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.shift = 28,
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.enc = BOOK3E_PAGESZ_256M,
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},
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[MMU_PAGE_1G] = {
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.shift = 30,
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.enc = BOOK3E_PAGESZ_1GB,
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},
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};
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#endif /* CONFIG_FSL_BOOKE */
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static inline int mmu_get_tsize(int psize)
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{
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return mmu_psize_defs[psize].enc;
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}
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#else
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static inline int mmu_get_tsize(int psize)
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{
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/* This isn't used on !Book3E for now */
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return 0;
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}
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#endif /* CONFIG_PPC_BOOK3E_MMU */
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/* The variables below are currently only used on 64-bit Book3E
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* though this will probably be made common with other nohash
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* implementations at some point
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*/
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#ifdef CONFIG_PPC64
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int mmu_linear_psize; /* Page size used for the linear mapping */
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int mmu_pte_psize; /* Page size used for PTE pages */
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int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
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int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
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unsigned long linear_map_top; /* Top of linear mapping */
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/*
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* Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug
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* exceptions. This is used for bolted and e6500 TLB miss handlers which
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* do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
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* this is set to zero.
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*/
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int extlb_level_exc;
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#endif /* CONFIG_PPC64 */
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#ifdef CONFIG_PPC_FSL_BOOK3E
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/* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
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DEFINE_PER_CPU(int, next_tlbcam_idx);
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EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
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#endif
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/*
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* Base TLB flushing operations:
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*
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes kernel pages
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*
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* - local_* variants of page and mm only apply to the current
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* processor
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*/
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/*
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* These are the base non-SMP variants of page and mm flushing
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*/
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned int pid;
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preempt_disable();
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pid = mm->context.id;
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if (pid != MMU_NO_CONTEXT)
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_tlbil_pid(pid);
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preempt_enable();
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}
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EXPORT_SYMBOL(local_flush_tlb_mm);
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void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
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int tsize, int ind)
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{
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unsigned int pid;
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preempt_disable();
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pid = mm ? mm->context.id : 0;
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if (pid != MMU_NO_CONTEXT)
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_tlbil_va(vmaddr, pid, tsize, ind);
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preempt_enable();
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}
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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__local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
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mmu_get_tsize(mmu_virtual_psize), 0);
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}
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EXPORT_SYMBOL(local_flush_tlb_page);
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/*
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* And here are the SMP non-local implementations
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*/
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#ifdef CONFIG_SMP
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static DEFINE_RAW_SPINLOCK(tlbivax_lock);
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static int mm_is_core_local(struct mm_struct *mm)
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{
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return cpumask_subset(mm_cpumask(mm),
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topology_thread_cpumask(smp_processor_id()));
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}
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struct tlb_flush_param {
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unsigned long addr;
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unsigned int pid;
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unsigned int tsize;
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unsigned int ind;
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};
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static void do_flush_tlb_mm_ipi(void *param)
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{
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struct tlb_flush_param *p = param;
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_tlbil_pid(p ? p->pid : 0);
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}
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static void do_flush_tlb_page_ipi(void *param)
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{
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struct tlb_flush_param *p = param;
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_tlbil_va(p->addr, p->pid, p->tsize, p->ind);
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}
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/* Note on invalidations and PID:
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*
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* We snapshot the PID with preempt disabled. At this point, it can still
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* change either because:
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* - our context is being stolen (PID -> NO_CONTEXT) on another CPU
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* - we are invaliating some target that isn't currently running here
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* and is concurrently acquiring a new PID on another CPU
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* - some other CPU is re-acquiring a lost PID for this mm
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* etc...
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*
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* However, this shouldn't be a problem as we only guarantee
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* invalidation of TLB entries present prior to this call, so we
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* don't care about the PID changing, and invalidating a stale PID
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* is generally harmless.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned int pid;
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preempt_disable();
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pid = mm->context.id;
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if (unlikely(pid == MMU_NO_CONTEXT))
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goto no_context;
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if (!mm_is_core_local(mm)) {
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struct tlb_flush_param p = { .pid = pid };
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/* Ignores smp_processor_id() even if set. */
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smp_call_function_many(mm_cpumask(mm),
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do_flush_tlb_mm_ipi, &p, 1);
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}
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_tlbil_pid(pid);
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no_context:
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preempt_enable();
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}
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EXPORT_SYMBOL(flush_tlb_mm);
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void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
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int tsize, int ind)
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{
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struct cpumask *cpu_mask;
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unsigned int pid;
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preempt_disable();
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pid = mm ? mm->context.id : 0;
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if (unlikely(pid == MMU_NO_CONTEXT))
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goto bail;
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cpu_mask = mm_cpumask(mm);
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if (!mm_is_core_local(mm)) {
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/* If broadcast tlbivax is supported, use it */
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if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
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int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
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if (lock)
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raw_spin_lock(&tlbivax_lock);
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_tlbivax_bcast(vmaddr, pid, tsize, ind);
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if (lock)
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raw_spin_unlock(&tlbivax_lock);
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goto bail;
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} else {
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struct tlb_flush_param p = {
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.pid = pid,
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.addr = vmaddr,
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.tsize = tsize,
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.ind = ind,
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};
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/* Ignores smp_processor_id() even if set in cpu_mask */
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smp_call_function_many(cpu_mask,
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do_flush_tlb_page_ipi, &p, 1);
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}
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}
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_tlbil_va(vmaddr, pid, tsize, ind);
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bail:
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preempt_enable();
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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#ifdef CONFIG_HUGETLB_PAGE
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if (vma && is_vm_hugetlb_page(vma))
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flush_hugetlb_page(vma, vmaddr);
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#endif
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__flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
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mmu_get_tsize(mmu_virtual_psize), 0);
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}
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EXPORT_SYMBOL(flush_tlb_page);
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_PPC_47x
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void __init early_init_mmu_47x(void)
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{
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#ifdef CONFIG_SMP
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unsigned long root = of_get_flat_dt_root();
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if (of_get_flat_dt_prop(root, "cooperative-partition", NULL))
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mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST);
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#endif /* CONFIG_SMP */
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}
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#endif /* CONFIG_PPC_47x */
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/*
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* Flush kernel TLB entries in the given range
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*/
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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#ifdef CONFIG_SMP
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preempt_disable();
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smp_call_function(do_flush_tlb_mm_ipi, NULL, 1);
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_tlbil_pid(0);
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preempt_enable();
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#else
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_tlbil_pid(0);
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#endif
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}
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EXPORT_SYMBOL(flush_tlb_kernel_range);
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/*
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* Currently, for range flushing, we just do a full mm flush. This should
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* be optimized based on a threshold on the size of the range, since
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* some implementation can stack multiple tlbivax before a tlbsync but
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* for now, we keep it that way
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*/
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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flush_tlb_mm(vma->vm_mm);
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}
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EXPORT_SYMBOL(flush_tlb_range);
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void tlb_flush(struct mmu_gather *tlb)
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{
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flush_tlb_mm(tlb->mm);
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}
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/*
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* Below are functions specific to the 64-bit variant of Book3E though that
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* may change in the future
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*/
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#ifdef CONFIG_PPC64
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/*
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* Handling of virtual linear page tables or indirect TLB entries
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* flushing when PTE pages are freed
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*/
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void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
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{
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int tsize = mmu_psize_defs[mmu_pte_psize].enc;
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if (book3e_htw_mode != PPC_HTW_NONE) {
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unsigned long start = address & PMD_MASK;
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unsigned long end = address + PMD_SIZE;
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unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
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/* This isn't the most optimal, ideally we would factor out the
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* while preempt & CPU mask mucking around, or even the IPI but
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* it will do for now
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*/
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while (start < end) {
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__flush_tlb_page(tlb->mm, start, tsize, 1);
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start += size;
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}
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} else {
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unsigned long rmask = 0xf000000000000000ul;
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unsigned long rid = (address & rmask) | 0x1000000000000000ul;
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unsigned long vpte = address & ~rmask;
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#ifdef CONFIG_PPC_64K_PAGES
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vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful;
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#else
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vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
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#endif
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vpte |= rid;
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__flush_tlb_page(tlb->mm, vpte, tsize, 0);
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}
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}
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|
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static void setup_page_sizes(void)
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{
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unsigned int tlb0cfg;
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unsigned int tlb0ps;
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unsigned int eptcfg;
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int i, psize;
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#ifdef CONFIG_PPC_FSL_BOOK3E
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unsigned int mmucfg = mfspr(SPRN_MMUCFG);
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int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
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if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
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unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
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unsigned int min_pg, max_pg;
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min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
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max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
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|
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for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
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struct mmu_psize_def *def;
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unsigned int shift;
|
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def = &mmu_psize_defs[psize];
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shift = def->shift;
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if (shift == 0 || shift & 1)
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continue;
|
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|
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/* adjust to be in terms of 4^shift Kb */
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shift = (shift - 10) >> 1;
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|
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if ((shift >= min_pg) && (shift <= max_pg))
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def->flags |= MMU_PAGE_SIZE_DIRECT;
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}
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|
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goto out;
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}
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if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
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u32 tlb1cfg, tlb1ps;
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tlb0cfg = mfspr(SPRN_TLB0CFG);
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tlb1cfg = mfspr(SPRN_TLB1CFG);
|
|
tlb1ps = mfspr(SPRN_TLB1PS);
|
|
eptcfg = mfspr(SPRN_EPTCFG);
|
|
|
|
if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
|
|
book3e_htw_mode = PPC_HTW_E6500;
|
|
|
|
/*
|
|
* We expect 4K subpage size and unrestricted indirect size.
|
|
* The lack of a restriction on indirect size is a Freescale
|
|
* extension, indicated by PSn = 0 but SPSn != 0.
|
|
*/
|
|
if (eptcfg != 2)
|
|
book3e_htw_mode = PPC_HTW_NONE;
|
|
|
|
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
|
|
struct mmu_psize_def *def = &mmu_psize_defs[psize];
|
|
|
|
if (tlb1ps & (1U << (def->shift - 10))) {
|
|
def->flags |= MMU_PAGE_SIZE_DIRECT;
|
|
|
|
if (book3e_htw_mode && psize == MMU_PAGE_2M)
|
|
def->flags |= MMU_PAGE_SIZE_INDIRECT;
|
|
}
|
|
}
|
|
|
|
goto out;
|
|
}
|
|
#endif
|
|
|
|
tlb0cfg = mfspr(SPRN_TLB0CFG);
|
|
tlb0ps = mfspr(SPRN_TLB0PS);
|
|
eptcfg = mfspr(SPRN_EPTCFG);
|
|
|
|
/* Look for supported direct sizes */
|
|
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
|
|
struct mmu_psize_def *def = &mmu_psize_defs[psize];
|
|
|
|
if (tlb0ps & (1U << (def->shift - 10)))
|
|
def->flags |= MMU_PAGE_SIZE_DIRECT;
|
|
}
|
|
|
|
/* Indirect page sizes supported ? */
|
|
if ((tlb0cfg & TLBnCFG_IND) == 0 ||
|
|
(tlb0cfg & TLBnCFG_PT) == 0)
|
|
goto out;
|
|
|
|
book3e_htw_mode = PPC_HTW_IBM;
|
|
|
|
/* Now, we only deal with one IND page size for each
|
|
* direct size. Hopefully all implementations today are
|
|
* unambiguous, but we might want to be careful in the
|
|
* future.
|
|
*/
|
|
for (i = 0; i < 3; i++) {
|
|
unsigned int ps, sps;
|
|
|
|
sps = eptcfg & 0x1f;
|
|
eptcfg >>= 5;
|
|
ps = eptcfg & 0x1f;
|
|
eptcfg >>= 5;
|
|
if (!ps || !sps)
|
|
continue;
|
|
for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
|
|
struct mmu_psize_def *def = &mmu_psize_defs[psize];
|
|
|
|
if (ps == (def->shift - 10))
|
|
def->flags |= MMU_PAGE_SIZE_INDIRECT;
|
|
if (sps == (def->shift - 10))
|
|
def->ind = ps + 10;
|
|
}
|
|
}
|
|
|
|
out:
|
|
/* Cleanup array and print summary */
|
|
pr_info("MMU: Supported page sizes\n");
|
|
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
|
|
struct mmu_psize_def *def = &mmu_psize_defs[psize];
|
|
const char *__page_type_names[] = {
|
|
"unsupported",
|
|
"direct",
|
|
"indirect",
|
|
"direct & indirect"
|
|
};
|
|
if (def->flags == 0) {
|
|
def->shift = 0;
|
|
continue;
|
|
}
|
|
pr_info(" %8ld KB as %s\n", 1ul << (def->shift - 10),
|
|
__page_type_names[def->flags & 0x3]);
|
|
}
|
|
}
|
|
|
|
static void setup_mmu_htw(void)
|
|
{
|
|
/*
|
|
* If we want to use HW tablewalk, enable it by patching the TLB miss
|
|
* handlers to branch to the one dedicated to it.
|
|
*/
|
|
|
|
switch (book3e_htw_mode) {
|
|
case PPC_HTW_IBM:
|
|
patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
|
|
patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
|
|
break;
|
|
#ifdef CONFIG_PPC_FSL_BOOK3E
|
|
case PPC_HTW_E6500:
|
|
extlb_level_exc = EX_TLB_SIZE;
|
|
patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
|
|
patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
|
|
break;
|
|
#endif
|
|
}
|
|
pr_info("MMU: Book3E HW tablewalk %s\n",
|
|
book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
|
|
}
|
|
|
|
/*
|
|
* Early initialization of the MMU TLB code
|
|
*/
|
|
static void __early_init_mmu(int boot_cpu)
|
|
{
|
|
unsigned int mas4;
|
|
|
|
/* XXX This will have to be decided at runtime, but right
|
|
* now our boot and TLB miss code hard wires it. Ideally
|
|
* we should find out a suitable page size and patch the
|
|
* TLB miss code (either that or use the PACA to store
|
|
* the value we want)
|
|
*/
|
|
mmu_linear_psize = MMU_PAGE_1G;
|
|
|
|
/* XXX This should be decided at runtime based on supported
|
|
* page sizes in the TLB, but for now let's assume 16M is
|
|
* always there and a good fit (which it probably is)
|
|
*
|
|
* Freescale booke only supports 4K pages in TLB0, so use that.
|
|
*/
|
|
if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
|
|
mmu_vmemmap_psize = MMU_PAGE_4K;
|
|
else
|
|
mmu_vmemmap_psize = MMU_PAGE_16M;
|
|
|
|
/* XXX This code only checks for TLB 0 capabilities and doesn't
|
|
* check what page size combos are supported by the HW. It
|
|
* also doesn't handle the case where a separate array holds
|
|
* the IND entries from the array loaded by the PT.
|
|
*/
|
|
if (boot_cpu) {
|
|
/* Look for supported page sizes */
|
|
setup_page_sizes();
|
|
|
|
/* Look for HW tablewalk support */
|
|
setup_mmu_htw();
|
|
}
|
|
|
|
/* Set MAS4 based on page table setting */
|
|
|
|
mas4 = 0x4 << MAS4_WIMGED_SHIFT;
|
|
switch (book3e_htw_mode) {
|
|
case PPC_HTW_E6500:
|
|
mas4 |= MAS4_INDD;
|
|
mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
|
|
mas4 |= MAS4_TLBSELD(1);
|
|
mmu_pte_psize = MMU_PAGE_2M;
|
|
break;
|
|
|
|
case PPC_HTW_IBM:
|
|
mas4 |= MAS4_INDD;
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
|
|
mmu_pte_psize = MMU_PAGE_256M;
|
|
#else
|
|
mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
|
|
mmu_pte_psize = MMU_PAGE_1M;
|
|
#endif
|
|
break;
|
|
|
|
case PPC_HTW_NONE:
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
|
|
#else
|
|
mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
|
|
#endif
|
|
mmu_pte_psize = mmu_virtual_psize;
|
|
break;
|
|
}
|
|
mtspr(SPRN_MAS4, mas4);
|
|
|
|
/* Set the global containing the top of the linear mapping
|
|
* for use by the TLB miss code
|
|
*/
|
|
linear_map_top = memblock_end_of_DRAM();
|
|
|
|
#ifdef CONFIG_PPC_FSL_BOOK3E
|
|
if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
|
|
unsigned int num_cams;
|
|
|
|
/* use a quarter of the TLBCAM for bolted linear map */
|
|
num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
|
|
linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
|
|
|
|
/* limit memory so we dont have linear faults */
|
|
memblock_enforce_memory_limit(linear_map_top);
|
|
|
|
if (book3e_htw_mode == PPC_HTW_NONE) {
|
|
extlb_level_exc = EX_TLB_SIZE;
|
|
patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
|
|
patch_exception(0x1e0,
|
|
exc_instruction_tlb_miss_bolted_book3e);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* A sync won't hurt us after mucking around with
|
|
* the MMU configuration
|
|
*/
|
|
mb();
|
|
|
|
memblock_set_current_limit(linear_map_top);
|
|
}
|
|
|
|
void __init early_init_mmu(void)
|
|
{
|
|
__early_init_mmu(1);
|
|
}
|
|
|
|
void early_init_mmu_secondary(void)
|
|
{
|
|
__early_init_mmu(0);
|
|
}
|
|
|
|
void setup_initial_memory_limit(phys_addr_t first_memblock_base,
|
|
phys_addr_t first_memblock_size)
|
|
{
|
|
/* On non-FSL Embedded 64-bit, we adjust the RMA size to match
|
|
* the bolted TLB entry. We know for now that only 1G
|
|
* entries are supported though that may eventually
|
|
* change.
|
|
*
|
|
* on FSL Embedded 64-bit, we adjust the RMA size to match the
|
|
* first bolted TLB entry size. We still limit max to 1G even if
|
|
* the TLB could cover more. This is due to what the early init
|
|
* code is setup to do.
|
|
*
|
|
* We crop it to the size of the first MEMBLOCK to
|
|
* avoid going over total available memory just in case...
|
|
*/
|
|
#ifdef CONFIG_PPC_FSL_BOOK3E
|
|
if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
|
|
unsigned long linear_sz;
|
|
linear_sz = calc_cam_sz(first_memblock_size, PAGE_OFFSET,
|
|
first_memblock_base);
|
|
ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
|
|
} else
|
|
#endif
|
|
ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
|
|
|
|
/* Finally limit subsequent allocations */
|
|
memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
|
|
}
|
|
#else /* ! CONFIG_PPC64 */
|
|
void __init early_init_mmu(void)
|
|
{
|
|
#ifdef CONFIG_PPC_47x
|
|
early_init_mmu_47x();
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_PPC64 */
|