![Geert Uytterhoeven](/assets/img/avatar_default.png)
Commit bcf24e1daa
("mmc: omap_hsmmc: use the generic config for
omap2plus devices"), enabled the build for other platforms for compile
testing.
sh-allmodconfig now fails with:
include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1
This happens because SuperH #defines "CCR", which is one of the enum
values in include/linux/omap-dma.h. There's a similar issue with "CCR2"
on sh2a.
As "CCR" and "CCR2" are too generic names for global #defines, prefix
them with "SH_" to fix this.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
395 lines
9.7 KiB
C
395 lines
9.7 KiB
C
/*
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* arch/sh/mm/cache-sh4.c
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*
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* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
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* Copyright (C) 2001 - 2009 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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* Copyright (c) 2007 STMicroelectronics (R&D) Ltd.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <linux/mutex.h>
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#include <linux/fs.h>
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#include <linux/highmem.h>
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#include <asm/pgtable.h>
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#include <asm/mmu_context.h>
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#include <asm/cache_insns.h>
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#include <asm/cacheflush.h>
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/*
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* The maximum number of pages we support up to when doing ranged dcache
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* flushing. Anything exceeding this will simply flush the dcache in its
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* entirety.
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*/
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#define MAX_ICACHE_PAGES 32
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static void __flush_cache_one(unsigned long addr, unsigned long phys,
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unsigned long exec_offset);
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/*
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* Write back the range of D-cache, and purge the I-cache.
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*
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* Called from kernel/module.c:sys_init_module and routine for a.out format,
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* signal handler code and kprobes code
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*/
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static void sh4_flush_icache_range(void *args)
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{
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struct flusher_data *data = args;
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unsigned long start, end;
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unsigned long flags, v;
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int i;
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start = data->addr1;
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end = data->addr2;
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/* If there are too many pages then just blow away the caches */
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if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
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local_flush_cache_all(NULL);
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return;
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}
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/*
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* Selectively flush d-cache then invalidate the i-cache.
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* This is inefficient, so only use this for small ranges.
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*/
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start &= ~(L1_CACHE_BYTES-1);
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end += L1_CACHE_BYTES-1;
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end &= ~(L1_CACHE_BYTES-1);
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local_irq_save(flags);
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jump_to_uncached();
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for (v = start; v < end; v += L1_CACHE_BYTES) {
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unsigned long icacheaddr;
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int j, n;
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__ocbwb(v);
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icacheaddr = CACHE_IC_ADDRESS_ARRAY | (v &
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cpu_data->icache.entry_mask);
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/* Clear i-cache line valid-bit */
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n = boot_cpu_data.icache.n_aliases;
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for (i = 0; i < cpu_data->icache.ways; i++) {
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for (j = 0; j < n; j++)
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__raw_writel(0, icacheaddr + (j * PAGE_SIZE));
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icacheaddr += cpu_data->icache.way_incr;
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}
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}
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back_to_cached();
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local_irq_restore(flags);
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}
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static inline void flush_cache_one(unsigned long start, unsigned long phys)
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{
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unsigned long flags, exec_offset = 0;
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/*
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* All types of SH-4 require PC to be uncached to operate on the I-cache.
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* Some types of SH-4 require PC to be uncached to operate on the D-cache.
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*/
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if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
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(start < CACHE_OC_ADDRESS_ARRAY))
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exec_offset = cached_to_uncached;
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local_irq_save(flags);
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__flush_cache_one(start, phys, exec_offset);
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local_irq_restore(flags);
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}
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/*
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* Write back & invalidate the D-cache of the page.
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* (To avoid "alias" issues)
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*/
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static void sh4_flush_dcache_page(void *arg)
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{
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struct page *page = arg;
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unsigned long addr = (unsigned long)page_address(page);
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#ifndef CONFIG_SMP
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struct address_space *mapping = page_mapping(page);
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if (mapping && !mapping_mapped(mapping))
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clear_bit(PG_dcache_clean, &page->flags);
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else
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#endif
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flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
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(addr & shm_align_mask), page_to_phys(page));
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wmb();
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}
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/* TODO: Selective icache invalidation through IC address array.. */
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static void flush_icache_all(void)
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{
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unsigned long flags, ccr;
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local_irq_save(flags);
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jump_to_uncached();
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/* Flush I-cache */
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ccr = __raw_readl(SH_CCR);
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ccr |= CCR_CACHE_ICI;
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__raw_writel(ccr, SH_CCR);
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/*
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* back_to_cached() will take care of the barrier for us, don't add
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* another one!
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*/
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back_to_cached();
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local_irq_restore(flags);
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}
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static void flush_dcache_all(void)
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{
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unsigned long addr, end_addr, entry_offset;
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end_addr = CACHE_OC_ADDRESS_ARRAY +
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(current_cpu_data.dcache.sets <<
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current_cpu_data.dcache.entry_shift) *
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current_cpu_data.dcache.ways;
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entry_offset = 1 << current_cpu_data.dcache.entry_shift;
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for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; ) {
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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}
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}
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static void sh4_flush_cache_all(void *unused)
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{
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flush_dcache_all();
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flush_icache_all();
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}
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/*
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* Note : (RPC) since the caches are physically tagged, the only point
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* of flush_cache_mm for SH-4 is to get rid of aliases from the
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* D-cache. The assumption elsewhere, e.g. flush_cache_range, is that
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* lines can stay resident so long as the virtual address they were
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* accessed with (hence cache set) is in accord with the physical
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* address (i.e. tag). It's no different here.
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*
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* Caller takes mm->mmap_sem.
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*/
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static void sh4_flush_cache_mm(void *arg)
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{
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struct mm_struct *mm = arg;
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if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT)
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return;
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flush_dcache_all();
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}
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/*
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* Write back and invalidate I/D-caches for the page.
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*
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* ADDR: Virtual Address (U0 address)
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* PFN: Physical page number
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*/
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static void sh4_flush_cache_page(void *args)
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{
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struct flusher_data *data = args;
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struct vm_area_struct *vma;
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struct page *page;
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unsigned long address, pfn, phys;
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int map_coherent = 0;
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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void *vaddr;
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vma = data->vma;
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address = data->addr1 & PAGE_MASK;
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pfn = data->addr2;
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phys = pfn << PAGE_SHIFT;
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page = pfn_to_page(pfn);
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if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
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return;
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pgd = pgd_offset(vma->vm_mm, address);
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pud = pud_offset(pgd, address);
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pmd = pmd_offset(pud, address);
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pte = pte_offset_kernel(pmd, address);
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/* If the page isn't present, there is nothing to do here. */
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if (!(pte_val(*pte) & _PAGE_PRESENT))
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return;
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if ((vma->vm_mm == current->active_mm))
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vaddr = NULL;
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else {
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/*
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* Use kmap_coherent or kmap_atomic to do flushes for
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* another ASID than the current one.
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*/
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map_coherent = (current_cpu_data.dcache.n_aliases &&
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test_bit(PG_dcache_clean, &page->flags) &&
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page_mapped(page));
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if (map_coherent)
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vaddr = kmap_coherent(page, address);
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else
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vaddr = kmap_atomic(page);
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address = (unsigned long)vaddr;
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}
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flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
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(address & shm_align_mask), phys);
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if (vma->vm_flags & VM_EXEC)
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flush_icache_all();
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if (vaddr) {
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if (map_coherent)
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kunmap_coherent(vaddr);
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else
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kunmap_atomic(vaddr);
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}
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}
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/*
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* Write back and invalidate D-caches.
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*
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* START, END: Virtual Address (U0 address)
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*
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* NOTE: We need to flush the _physical_ page entry.
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* Flushing the cache lines for U0 only isn't enough.
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* We need to flush for P1 too, which may contain aliases.
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*/
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static void sh4_flush_cache_range(void *args)
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{
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struct flusher_data *data = args;
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struct vm_area_struct *vma;
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unsigned long start, end;
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vma = data->vma;
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start = data->addr1;
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end = data->addr2;
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if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
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return;
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/*
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* If cache is only 4k-per-way, there are never any 'aliases'. Since
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* the cache is physically tagged, the data can just be left in there.
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*/
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if (boot_cpu_data.dcache.n_aliases == 0)
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return;
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flush_dcache_all();
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if (vma->vm_flags & VM_EXEC)
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flush_icache_all();
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}
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/**
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* __flush_cache_one
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*
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* @addr: address in memory mapped cache array
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* @phys: P1 address to flush (has to match tags if addr has 'A' bit
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* set i.e. associative write)
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* @exec_offset: set to 0x20000000 if flush has to be executed from P2
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* region else 0x0
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*
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* The offset into the cache array implied by 'addr' selects the
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* 'colour' of the virtual address range that will be flushed. The
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* operation (purge/write-back) is selected by the lower 2 bits of
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* 'phys'.
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*/
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static void __flush_cache_one(unsigned long addr, unsigned long phys,
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unsigned long exec_offset)
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{
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int way_count;
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unsigned long base_addr = addr;
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struct cache_info *dcache;
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unsigned long way_incr;
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unsigned long a, ea, p;
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unsigned long temp_pc;
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dcache = &boot_cpu_data.dcache;
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/* Write this way for better assembly. */
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way_count = dcache->ways;
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way_incr = dcache->way_incr;
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/*
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* Apply exec_offset (i.e. branch to P2 if required.).
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*
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* FIXME:
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*
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* If I write "=r" for the (temp_pc), it puts this in r6 hence
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* trashing exec_offset before it's been added on - why? Hence
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* "=&r" as a 'workaround'
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*/
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asm volatile("mov.l 1f, %0\n\t"
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"add %1, %0\n\t"
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"jmp @%0\n\t"
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"nop\n\t"
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".balign 4\n\t"
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"1: .long 2f\n\t"
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"2:\n" : "=&r" (temp_pc) : "r" (exec_offset));
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/*
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* We know there will be >=1 iteration, so write as do-while to avoid
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* pointless nead-of-loop check for 0 iterations.
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*/
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do {
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ea = base_addr + PAGE_SIZE;
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a = base_addr;
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p = phys;
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do {
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*(volatile unsigned long *)a = p;
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/*
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* Next line: intentionally not p+32, saves an add, p
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* will do since only the cache tag bits need to
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* match.
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*/
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*(volatile unsigned long *)(a+32) = p;
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a += 64;
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p += 64;
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} while (a < ea);
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base_addr += way_incr;
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} while (--way_count != 0);
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}
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extern void __weak sh4__flush_region_init(void);
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/*
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* SH-4 has virtually indexed and physically tagged cache.
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*/
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void __init sh4_cache_init(void)
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{
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printk("PVR=%08x CVR=%08x PRR=%08x\n",
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__raw_readl(CCN_PVR),
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__raw_readl(CCN_CVR),
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__raw_readl(CCN_PRR));
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local_flush_icache_range = sh4_flush_icache_range;
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local_flush_dcache_page = sh4_flush_dcache_page;
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local_flush_cache_all = sh4_flush_cache_all;
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local_flush_cache_mm = sh4_flush_cache_mm;
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local_flush_cache_dup_mm = sh4_flush_cache_mm;
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local_flush_cache_page = sh4_flush_cache_page;
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local_flush_cache_range = sh4_flush_cache_range;
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sh4__flush_region_init();
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}
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