![Paul Gortmaker](/assets/img/avatar_default.png)
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0
("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/sh uses of the __cpuinit macros from
all C files. Currently sh does not have any __CPUINIT used in
assembly files.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
225 lines
5.5 KiB
C
225 lines
5.5 KiB
C
/*
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* arch/sh/mm/tlb-sh5.c
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*
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* Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
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* Copyright (C) 2003 Richard Curnow <richard.curnow@superh.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <asm/page.h>
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#include <asm/tlb.h>
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#include <asm/mmu_context.h>
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/**
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* sh64_tlb_init - Perform initial setup for the DTLB and ITLB.
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*/
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int sh64_tlb_init(void)
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{
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/* Assign some sane DTLB defaults */
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cpu_data->dtlb.entries = 64;
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cpu_data->dtlb.step = 0x10;
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cpu_data->dtlb.first = DTLB_FIXED | cpu_data->dtlb.step;
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cpu_data->dtlb.next = cpu_data->dtlb.first;
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cpu_data->dtlb.last = DTLB_FIXED |
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((cpu_data->dtlb.entries - 1) *
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cpu_data->dtlb.step);
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/* And again for the ITLB */
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cpu_data->itlb.entries = 64;
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cpu_data->itlb.step = 0x10;
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cpu_data->itlb.first = ITLB_FIXED | cpu_data->itlb.step;
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cpu_data->itlb.next = cpu_data->itlb.first;
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cpu_data->itlb.last = ITLB_FIXED |
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((cpu_data->itlb.entries - 1) *
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cpu_data->itlb.step);
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return 0;
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}
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/**
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* sh64_next_free_dtlb_entry - Find the next available DTLB entry
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*/
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unsigned long long sh64_next_free_dtlb_entry(void)
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{
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return cpu_data->dtlb.next;
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}
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/**
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* sh64_get_wired_dtlb_entry - Allocate a wired (locked-in) entry in the DTLB
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*/
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unsigned long long sh64_get_wired_dtlb_entry(void)
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{
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unsigned long long entry = sh64_next_free_dtlb_entry();
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cpu_data->dtlb.first += cpu_data->dtlb.step;
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cpu_data->dtlb.next += cpu_data->dtlb.step;
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return entry;
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}
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/**
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* sh64_put_wired_dtlb_entry - Free a wired (locked-in) entry in the DTLB.
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*
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* @entry: Address of TLB slot.
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*
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* Works like a stack, last one to allocate must be first one to free.
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*/
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int sh64_put_wired_dtlb_entry(unsigned long long entry)
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{
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__flush_tlb_slot(entry);
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/*
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* We don't do any particularly useful tracking of wired entries,
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* so this approach works like a stack .. last one to be allocated
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* has to be the first one to be freed.
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*
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* We could potentially load wired entries into a list and work on
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* rebalancing the list periodically (which also entails moving the
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* contents of a TLB entry) .. though I have a feeling that this is
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* more trouble than it's worth.
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*/
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/*
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* Entry must be valid .. we don't want any ITLB addresses!
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*/
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if (entry <= DTLB_FIXED)
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return -EINVAL;
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/*
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* Next, check if we're within range to be freed. (ie, must be the
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* entry beneath the first 'free' entry!
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*/
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if (entry < (cpu_data->dtlb.first - cpu_data->dtlb.step))
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return -EINVAL;
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/* If we are, then bring this entry back into the list */
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cpu_data->dtlb.first -= cpu_data->dtlb.step;
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cpu_data->dtlb.next = entry;
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return 0;
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}
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/**
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* sh64_setup_tlb_slot - Load up a translation in a wired slot.
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*
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* @config_addr: Address of TLB slot.
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* @eaddr: Virtual address.
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* @asid: Address Space Identifier.
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* @paddr: Physical address.
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*
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* Load up a virtual<->physical translation for @eaddr<->@paddr in the
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* pre-allocated TLB slot @config_addr (see sh64_get_wired_dtlb_entry).
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*/
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void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
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unsigned long asid, unsigned long paddr)
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{
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unsigned long long pteh, ptel;
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pteh = neff_sign_extend(eaddr);
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pteh &= PAGE_MASK;
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pteh |= (asid << PTEH_ASID_SHIFT) | PTEH_VALID;
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ptel = neff_sign_extend(paddr);
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ptel &= PAGE_MASK;
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ptel |= (_PAGE_CACHABLE | _PAGE_READ | _PAGE_WRITE);
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asm volatile("putcfg %0, 1, %1\n\t"
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"putcfg %0, 0, %2\n"
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: : "r" (config_addr), "r" (ptel), "r" (pteh));
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}
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/**
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* sh64_teardown_tlb_slot - Teardown a translation.
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*
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* @config_addr: Address of TLB slot.
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*
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* Teardown any existing mapping in the TLB slot @config_addr.
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*/
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void sh64_teardown_tlb_slot(unsigned long long config_addr)
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__attribute__ ((alias("__flush_tlb_slot")));
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static int dtlb_entry;
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static unsigned long long dtlb_entries[64];
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void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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{
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unsigned long long entry;
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unsigned long paddr, flags;
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BUG_ON(dtlb_entry == ARRAY_SIZE(dtlb_entries));
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local_irq_save(flags);
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entry = sh64_get_wired_dtlb_entry();
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dtlb_entries[dtlb_entry++] = entry;
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paddr = pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK;
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paddr &= ~PAGE_MASK;
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sh64_setup_tlb_slot(entry, addr, get_asid(), paddr);
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local_irq_restore(flags);
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}
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void tlb_unwire_entry(void)
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{
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unsigned long long entry;
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unsigned long flags;
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BUG_ON(!dtlb_entry);
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local_irq_save(flags);
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entry = dtlb_entries[dtlb_entry--];
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sh64_teardown_tlb_slot(entry);
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sh64_put_wired_dtlb_entry(entry);
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local_irq_restore(flags);
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}
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void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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unsigned long long ptel;
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unsigned long long pteh=0;
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struct tlb_info *tlbp;
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unsigned long long next;
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unsigned int fault_code = get_thread_fault_code();
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/* Get PTEL first */
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ptel = pte.pte_low;
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/*
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* Set PTEH register
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*/
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pteh = neff_sign_extend(address & MMU_VPN_MASK);
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/* Set the ASID. */
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pteh |= get_asid() << PTEH_ASID_SHIFT;
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pteh |= PTEH_VALID;
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/* Set PTEL register, set_pte has performed the sign extension */
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ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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if (fault_code & FAULT_CODE_ITLB)
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tlbp = &cpu_data->itlb;
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else
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tlbp = &cpu_data->dtlb;
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next = tlbp->next;
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__flush_tlb_slot(next);
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asm volatile ("putcfg %0,1,%2\n\n\t"
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"putcfg %0,0,%1\n"
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: : "r" (next), "r" (pteh), "r" (ptel) );
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next += TLB_STEP;
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if (next > tlbp->last)
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next = tlbp->first;
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tlbp->next = next;
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}
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