91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* aQuantia Corporation Network Driver
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* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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*/
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/* File hw_atl_a0_internal.h: Definition of Atlantic A0 chip specific
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* constants.
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*/
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#ifndef HW_ATL_A0_INTERNAL_H
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#define HW_ATL_A0_INTERNAL_H
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#include "../aq_common.h"
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#define HW_ATL_A0_MTU_JUMBO 9014U
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#define HW_ATL_A0_TX_RINGS 4U
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#define HW_ATL_A0_RX_RINGS 4U
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#define HW_ATL_A0_RINGS_MAX 32U
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#define HW_ATL_A0_TXD_SIZE 16U
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#define HW_ATL_A0_RXD_SIZE 16U
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#define HW_ATL_A0_MAC 0U
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#define HW_ATL_A0_MAC_MIN 1U
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#define HW_ATL_A0_MAC_MAX 33U
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/* interrupts */
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#define HW_ATL_A0_ERR_INT 8U
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#define HW_ATL_A0_INT_MASK 0xFFFFFFFFU
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#define HW_ATL_A0_TXD_CTL2_LEN 0xFFFFC000U
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#define HW_ATL_A0_TXD_CTL2_CTX_EN 0x00002000U
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#define HW_ATL_A0_TXD_CTL2_CTX_IDX 0x00001000U
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#define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD 0x00000001U
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#define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC 0x00000002U
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#define HW_ATL_A0_TXD_CTL_BLEN 0x000FFFF0U
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#define HW_ATL_A0_TXD_CTL_DD 0x00100000U
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#define HW_ATL_A0_TXD_CTL_EOP 0x00200000U
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#define HW_ATL_A0_TXD_CTL_CMD_X 0x3FC00000U
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#define HW_ATL_A0_TXD_CTL_CMD_VLAN BIT(22)
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#define HW_ATL_A0_TXD_CTL_CMD_FCS BIT(23)
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#define HW_ATL_A0_TXD_CTL_CMD_IPCSO BIT(24)
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#define HW_ATL_A0_TXD_CTL_CMD_TUCSO BIT(25)
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#define HW_ATL_A0_TXD_CTL_CMD_LSO BIT(26)
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#define HW_ATL_A0_TXD_CTL_CMD_WB BIT(27)
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#define HW_ATL_A0_TXD_CTL_CMD_VXLAN BIT(28)
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#define HW_ATL_A0_TXD_CTL_CMD_IPV6 BIT(21)
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#define HW_ATL_A0_TXD_CTL_CMD_TCP BIT(22)
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#define HW_ATL_A0_MPI_CONTROL_ADR 0x0368U
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#define HW_ATL_A0_MPI_STATE_ADR 0x036CU
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#define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU
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#define HW_ATL_A0_MPI_SPEED_SHIFT 16U
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#define HW_ATL_A0_TXBUF_MAX 160U
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#define HW_ATL_A0_RXBUF_MAX 320U
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#define HW_ATL_A0_RSS_REDIRECTION_MAX 64U
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#define HW_ATL_A0_RSS_REDIRECTION_BITS 3U
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#define HW_ATL_A0_TC_MAX 1U
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#define HW_ATL_A0_RSS_MAX 8U
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#define HW_ATL_A0_FW_SEMA_RAM 0x2U
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#define HW_ATL_A0_RXD_DD 0x1U
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#define HW_ATL_A0_RXD_NCEA0 0x1U
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#define HW_ATL_A0_RXD_WB_STAT2_EOP 0x0002U
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#define HW_ATL_A0_UCP_0X370_REG 0x370U
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#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
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#define HW_ATL_A0_MIN_RXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))
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#define HW_ATL_A0_MIN_TXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))
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#define HW_ATL_A0_MAX_RXD 8184U
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#define HW_ATL_A0_MAX_TXD 8184U
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#endif /* HW_ATL_A0_INTERNAL_H */
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