489 lines
10 KiB
C
489 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* aQuantia Corporation Network Driver
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* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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*/
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/* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
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* abstraction layer.
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*/
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#ifndef HW_ATL_UTILS_H
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#define HW_ATL_UTILS_H
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#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
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/* Hardware tx descriptor */
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struct __packed hw_atl_txd_s {
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u64 buf_addr;
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u32 ctl;
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u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
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};
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/* Hardware tx context descriptor */
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struct __packed hw_atl_txc_s {
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u32 rsvd;
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u32 len;
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u32 ctl;
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u32 len2;
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};
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/* Hardware rx descriptor */
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struct __packed hw_atl_rxd_s {
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u64 buf_addr;
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u64 hdr_addr;
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};
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/* Hardware rx descriptor writeback */
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struct __packed hw_atl_rxd_wb_s {
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u32 type;
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u32 rss_hash;
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u16 status;
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u16 pkt_len;
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u16 next_desc_ptr;
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u16 vlan;
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};
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struct __packed hw_atl_stats_s {
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u32 uprc;
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u32 mprc;
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u32 bprc;
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u32 erpt;
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u32 uptc;
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u32 mptc;
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u32 bptc;
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u32 erpr;
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u32 mbtc;
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u32 bbtc;
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u32 mbrc;
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u32 bbrc;
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u32 ubrc;
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u32 ubtc;
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u32 dpc;
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};
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union __packed ip_addr {
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struct {
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u8 addr[16];
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} v6;
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struct {
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u8 padding[12];
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u8 addr[4];
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} v4;
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};
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struct __packed hw_atl_utils_fw_rpc {
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u32 msg_id;
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union {
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struct {
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u32 pong;
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} msg_ping;
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struct {
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u8 mac_addr[6];
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u32 ip_addr_cnt;
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struct {
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union ip_addr addr;
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union ip_addr mask;
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} ip[1];
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} msg_arp;
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struct {
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u32 len;
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u8 packet[1514U];
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} msg_inject;
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struct {
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u32 priority;
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u32 wol_packet_type;
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u32 pattern_id;
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u32 next_wol_pattern_offset;
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union {
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struct {
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u32 flags;
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u8 ipv4_source_address[4];
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u8 ipv4_dest_address[4];
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u16 tcp_source_port_number;
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u16 tcp_dest_port_number;
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} ipv4_tcp_syn_parameters;
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struct {
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u32 flags;
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u8 ipv6_source_address[16];
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u8 ipv6_dest_address[16];
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u16 tcp_source_port_number;
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u16 tcp_dest_port_number;
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} ipv6_tcp_syn_parameters;
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struct {
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u32 flags;
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} eapol_request_id_message_parameters;
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struct {
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u32 flags;
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u32 mask_offset;
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u32 mask_size;
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u32 pattern_offset;
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u32 pattern_size;
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} wol_bit_map_pattern;
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struct {
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u8 mac_addr[ETH_ALEN];
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} wol_magic_packet_patter;
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} wol_pattern;
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} msg_wol;
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struct {
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union {
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u32 pattern_mask;
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struct {
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u32 reason_arp_v4_pkt : 1;
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u32 reason_ipv4_ping_pkt : 1;
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u32 reason_ipv6_ns_pkt : 1;
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u32 reason_ipv6_ping_pkt : 1;
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u32 reason_link_up : 1;
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u32 reason_link_down : 1;
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u32 reason_maximum : 1;
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};
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};
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union {
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u32 offload_mask;
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};
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} msg_enable_wakeup;
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struct {
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u32 id;
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} msg_del_id;
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};
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};
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struct __packed hw_atl_utils_mbox_header {
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u32 version;
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u32 transaction_id;
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u32 error;
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};
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struct __packed hw_aq_info {
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u8 reserved[6];
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u16 phy_fault_code;
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u16 phy_temperature;
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u8 cable_len;
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u8 reserved1;
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u32 cable_diag_data[4];
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u8 reserved2[32];
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u32 caps_lo;
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u32 caps_hi;
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};
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struct __packed hw_atl_utils_mbox {
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struct hw_atl_utils_mbox_header header;
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struct hw_atl_stats_s stats;
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struct hw_aq_info info;
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};
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/* fw2x */
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typedef u32 fw_offset_t;
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struct __packed offload_ip_info {
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u8 v4_local_addr_count;
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u8 v4_addr_count;
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u8 v6_local_addr_count;
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u8 v6_addr_count;
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fw_offset_t v4_addr;
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fw_offset_t v4_prefix;
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fw_offset_t v6_addr;
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fw_offset_t v6_prefix;
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};
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struct __packed offload_port_info {
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u16 udp_port_count;
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u16 tcp_port_count;
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fw_offset_t udp_port;
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fw_offset_t tcp_port;
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};
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struct __packed offload_ka_info {
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u16 v4_ka_count;
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u16 v6_ka_count;
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u32 retry_count;
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u32 retry_interval;
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fw_offset_t v4_ka;
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fw_offset_t v6_ka;
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};
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struct __packed offload_rr_info {
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u32 rr_count;
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u32 rr_buf_len;
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fw_offset_t rr_id_x;
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fw_offset_t rr_buf;
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};
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struct __packed offload_info {
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u32 version;
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u32 len;
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u8 mac_addr[ETH_ALEN];
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u8 reserved[2];
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struct offload_ip_info ips;
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struct offload_port_info ports;
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struct offload_ka_info kas;
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struct offload_rr_info rrs;
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u8 buf[0];
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};
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enum hw_atl_rx_action_with_traffic {
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HW_ATL_RX_DISCARD,
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HW_ATL_RX_HOST,
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};
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struct aq_rx_filter_vlan {
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u8 enable;
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u8 location;
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u16 vlan_id;
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u8 queue;
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};
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struct aq_rx_filter_l2 {
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s8 queue;
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u8 location;
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u8 user_priority_en;
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u8 user_priority;
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u16 ethertype;
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};
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struct aq_rx_filter_l3l4 {
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u32 cmd;
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u8 location;
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u32 ip_dst[4];
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u32 ip_src[4];
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u16 p_dst;
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u16 p_src;
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u8 is_ipv6;
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};
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enum hw_atl_rx_protocol_value_l3l4 {
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HW_ATL_RX_TCP,
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HW_ATL_RX_UDP,
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HW_ATL_RX_SCTP,
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HW_ATL_RX_ICMP
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};
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enum hw_atl_rx_ctrl_registers_l3l4 {
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HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4 = BIT(22),
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HW_ATL_RX_ENABLE_QUEUE_L3L4 = BIT(23),
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HW_ATL_RX_ENABLE_ARP_FLTR_L3 = BIT(24),
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HW_ATL_RX_ENABLE_CMP_PROT_L4 = BIT(25),
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HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 = BIT(26),
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HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4 = BIT(27),
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HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3 = BIT(28),
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HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3 = BIT(29),
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HW_ATL_RX_ENABLE_L3_IPV6 = BIT(30),
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HW_ATL_RX_ENABLE_FLTR_L3L4 = BIT(31)
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};
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#define HW_ATL_RX_QUEUE_FL3L4_SHIFT 8U
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#define HW_ATL_RX_ACTION_FL3F4_SHIFT 16U
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#define HW_ATL_RX_CNT_REG_ADDR_IPV6 4U
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#define HW_ATL_GET_REG_LOCATION_FL3L4(location) \
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((location) - AQ_RX_FIRST_LOC_FL3L4)
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#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U
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#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U
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#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U
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#define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U
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#define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U
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#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
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#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U
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#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
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self->chip_features)
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enum hal_atl_utils_fw_state_e {
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MPI_DEINIT = 0,
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MPI_RESET = 1,
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MPI_INIT = 2,
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MPI_POWER = 4,
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};
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#define HAL_ATLANTIC_RATE_10G BIT(0)
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#define HAL_ATLANTIC_RATE_5G BIT(1)
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#define HAL_ATLANTIC_RATE_5GSR BIT(2)
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#define HAL_ATLANTIC_RATE_2GS BIT(3)
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#define HAL_ATLANTIC_RATE_1G BIT(4)
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#define HAL_ATLANTIC_RATE_100M BIT(5)
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#define HAL_ATLANTIC_RATE_INVALID BIT(6)
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#define HAL_ATLANTIC_UTILS_FW_MSG_PING 0x1U
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#define HAL_ATLANTIC_UTILS_FW_MSG_ARP 0x2U
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#define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 0x3U
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#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 0x4U
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#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PRIOR 0x10000000U
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#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PATTERN 0x1U
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#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_MAG_PKT 0x2U
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#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 0x5U
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#define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 0x6U
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#define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 0x7U
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#define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 0x8U
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#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 0x9U
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#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 0xAU
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#define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 0xDU
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enum hw_atl_fw2x_rate {
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FW2X_RATE_100M = 0x20,
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FW2X_RATE_1G = 0x100,
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FW2X_RATE_2G5 = 0x200,
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FW2X_RATE_5G = 0x400,
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FW2X_RATE_10G = 0x800,
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};
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enum hw_atl_fw2x_caps_lo {
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CAPS_LO_10BASET_HD = 0x00,
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CAPS_LO_10BASET_FD,
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CAPS_LO_100BASETX_HD,
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CAPS_LO_100BASET4_HD,
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CAPS_LO_100BASET2_HD,
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CAPS_LO_100BASETX_FD,
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CAPS_LO_100BASET2_FD,
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CAPS_LO_1000BASET_HD,
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CAPS_LO_1000BASET_FD,
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CAPS_LO_2P5GBASET_FD,
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CAPS_LO_5GBASET_FD,
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CAPS_LO_10GBASET_FD,
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};
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enum hw_atl_fw2x_caps_hi {
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CAPS_HI_RESERVED1 = 0x00,
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CAPS_HI_10BASET_EEE,
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CAPS_HI_RESERVED2,
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CAPS_HI_PAUSE,
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CAPS_HI_ASYMMETRIC_PAUSE,
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CAPS_HI_100BASETX_EEE,
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CAPS_HI_RESERVED3,
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CAPS_HI_RESERVED4,
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CAPS_HI_1000BASET_FD_EEE,
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CAPS_HI_2P5GBASET_FD_EEE,
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CAPS_HI_5GBASET_FD_EEE,
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CAPS_HI_10GBASET_FD_EEE,
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CAPS_HI_RESERVED5,
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CAPS_HI_RESERVED6,
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CAPS_HI_RESERVED7,
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CAPS_HI_RESERVED8,
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CAPS_HI_RESERVED9,
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CAPS_HI_CABLE_DIAG,
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CAPS_HI_TEMPERATURE,
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CAPS_HI_DOWNSHIFT,
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CAPS_HI_PTP_AVB_EN,
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CAPS_HI_MEDIA_DETECT,
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CAPS_HI_LINK_DROP,
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CAPS_HI_SLEEP_PROXY,
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CAPS_HI_WOL,
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CAPS_HI_MAC_STOP,
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CAPS_HI_EXT_LOOPBACK,
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CAPS_HI_INT_LOOPBACK,
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CAPS_HI_EFUSE_AGENT,
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CAPS_HI_WOL_TIMER,
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CAPS_HI_STATISTICS,
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CAPS_HI_TRANSACTION_ID,
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};
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enum hw_atl_fw2x_ctrl {
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CTRL_RESERVED1 = 0x00,
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CTRL_RESERVED2,
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CTRL_RESERVED3,
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CTRL_PAUSE,
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CTRL_ASYMMETRIC_PAUSE,
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CTRL_RESERVED4,
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CTRL_RESERVED5,
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CTRL_RESERVED6,
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CTRL_1GBASET_FD_EEE,
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CTRL_2P5GBASET_FD_EEE,
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CTRL_5GBASET_FD_EEE,
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CTRL_10GBASET_FD_EEE,
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CTRL_THERMAL_SHUTDOWN,
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CTRL_PHY_LOGS,
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CTRL_EEE_AUTO_DISABLE,
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CTRL_PFC,
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CTRL_WAKE_ON_LINK,
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CTRL_CABLE_DIAG,
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CTRL_TEMPERATURE,
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CTRL_DOWNSHIFT,
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CTRL_PTP_AVB,
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CTRL_RESERVED7,
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CTRL_LINK_DROP,
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CTRL_SLEEP_PROXY,
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CTRL_WOL,
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CTRL_MAC_STOP,
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CTRL_EXT_LOOPBACK,
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CTRL_INT_LOOPBACK,
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CTRL_RESERVED8,
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CTRL_WOL_TIMER,
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CTRL_STATISTICS,
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CTRL_FORCE_RECONNECT,
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};
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struct aq_hw_s;
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struct aq_fw_ops;
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struct aq_hw_caps_s;
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struct aq_hw_link_status_s;
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int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
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int hw_atl_utils_soft_reset(struct aq_hw_s *self);
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void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
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int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
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struct hw_atl_utils_mbox_header *pmbox);
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void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
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struct hw_atl_utils_mbox *pmbox);
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void hw_atl_utils_mpi_set(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state,
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u32 speed);
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int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
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int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
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u8 *mac);
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unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
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int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
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const struct aq_hw_caps_s *aq_hw_caps,
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u32 *regs_buff);
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int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
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unsigned int power_state);
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int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
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int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
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int hw_atl_utils_update_stats(struct aq_hw_s *self);
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struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
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int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
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u32 *p, u32 cnt);
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int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac);
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int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
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int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
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struct hw_atl_utils_fw_rpc **rpc);
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extern const struct aq_fw_ops aq_fw_1x_ops;
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extern const struct aq_fw_ops aq_fw_2x_ops;
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#endif /* HW_ATL_UTILS_H */
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