![Christoph Hellwig](/assets/img/avatar_default.png)
pci_enable_msix has been long deprecated, but this driver adds a new instance. Convert it to pci_alloc_irq_vectors and greatly simplify the code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
671 lines
17 KiB
C
671 lines
17 KiB
C
/*
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* Copyright (C) 2016 Cavium, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*/
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#include <linux/device.h>
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#include <linux/firmware.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/printk.h>
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#include <linux/version.h>
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#include "cptpf.h"
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#define DRV_NAME "thunder-cpt"
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#define DRV_VERSION "1.0"
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static u32 num_vfs = 4; /* Default 4 VF enabled */
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module_param(num_vfs, uint, 0444);
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MODULE_PARM_DESC(num_vfs, "Number of VFs to enable(1-16)");
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/*
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* Disable cores specified by coremask
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*/
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static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask,
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u8 type, u8 grp)
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{
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u64 pf_exe_ctl;
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u32 timeout = 100;
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u64 grpmask = 0;
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struct device *dev = &cpt->pdev->dev;
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if (type == AE_TYPES)
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coremask = (coremask << cpt->max_se_cores);
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/* Disengage the cores from groups */
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grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));
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cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),
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(grpmask & ~coremask));
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udelay(CSR_DELAY);
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grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));
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while (grp & coremask) {
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dev_err(dev, "Cores still busy %llx", coremask);
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grp = cpt_read_csr64(cpt->reg_base,
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CPTX_PF_EXEC_BUSY(0));
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if (timeout--)
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break;
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udelay(CSR_DELAY);
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}
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/* Disable the cores */
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pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));
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cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),
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(pf_exe_ctl & ~coremask));
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udelay(CSR_DELAY);
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}
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/*
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* Enable cores specified by coremask
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*/
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static void cpt_enable_cores(struct cpt_device *cpt, u64 coremask,
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u8 type)
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{
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u64 pf_exe_ctl;
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if (type == AE_TYPES)
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coremask = (coremask << cpt->max_se_cores);
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pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));
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cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),
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(pf_exe_ctl | coremask));
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udelay(CSR_DELAY);
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}
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static void cpt_configure_group(struct cpt_device *cpt, u8 grp,
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u64 coremask, u8 type)
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{
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u64 pf_gx_en = 0;
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if (type == AE_TYPES)
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coremask = (coremask << cpt->max_se_cores);
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pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));
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cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),
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(pf_gx_en | coremask));
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udelay(CSR_DELAY);
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}
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static void cpt_disable_mbox_interrupts(struct cpt_device *cpt)
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{
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/* Clear mbox(0) interupts for all vfs */
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cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull);
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}
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static void cpt_disable_ecc_interrupts(struct cpt_device *cpt)
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{
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/* Clear ecc(0) interupts for all vfs */
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cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull);
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}
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static void cpt_disable_exec_interrupts(struct cpt_device *cpt)
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{
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/* Clear exec interupts for all vfs */
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cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull);
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}
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static void cpt_disable_all_interrupts(struct cpt_device *cpt)
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{
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cpt_disable_mbox_interrupts(cpt);
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cpt_disable_ecc_interrupts(cpt);
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cpt_disable_exec_interrupts(cpt);
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}
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static void cpt_enable_mbox_interrupts(struct cpt_device *cpt)
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{
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/* Set mbox(0) interupts for all vfs */
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cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull);
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}
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static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
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{
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int ret = 0, core = 0, shift = 0;
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u32 total_cores = 0;
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struct device *dev = &cpt->pdev->dev;
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if (!mcode || !mcode->code) {
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dev_err(dev, "Either the mcode is null or data is NULL\n");
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return -EINVAL;
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}
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if (mcode->code_size == 0) {
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dev_err(dev, "microcode size is 0\n");
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return -EINVAL;
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}
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/* Assumes 0-9 are SE cores for UCODE_BASE registers and
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* AE core bases follow
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*/
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if (mcode->is_ae) {
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core = CPT_MAX_SE_CORES; /* start couting from 10 */
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total_cores = CPT_MAX_TOTAL_CORES; /* upto 15 */
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} else {
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core = 0; /* start couting from 0 */
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total_cores = CPT_MAX_SE_CORES; /* upto 9 */
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}
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/* Point to microcode for each core of the group */
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for (; core < total_cores ; core++, shift++) {
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if (mcode->core_mask & (1 << shift)) {
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cpt_write_csr64(cpt->reg_base,
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CPTX_PF_ENGX_UCODE_BASE(0, core),
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(u64)mcode->phys_base);
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}
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}
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return ret;
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}
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static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode)
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{
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int ret = 0;
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struct device *dev = &cpt->pdev->dev;
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/* Make device not ready */
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cpt->flags &= ~CPT_FLAG_DEVICE_READY;
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/* Disable All PF interrupts */
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cpt_disable_all_interrupts(cpt);
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/* Calculate mcode group and coremasks */
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if (mcode->is_ae) {
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if (mcode->num_cores > cpt->max_ae_cores) {
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dev_err(dev, "Requested for more cores than available AE cores\n");
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ret = -EINVAL;
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goto cpt_init_fail;
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}
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if (cpt->next_group >= CPT_MAX_CORE_GROUPS) {
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dev_err(dev, "Can't load, all eight microcode groups in use");
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return -ENFILE;
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}
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mcode->group = cpt->next_group;
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/* Convert requested cores to mask */
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mcode->core_mask = GENMASK(mcode->num_cores, 0);
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cpt_disable_cores(cpt, mcode->core_mask, AE_TYPES,
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mcode->group);
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/* Load microcode for AE engines */
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ret = cpt_load_microcode(cpt, mcode);
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if (ret) {
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dev_err(dev, "Microcode load Failed for %s\n",
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mcode->version);
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goto cpt_init_fail;
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}
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cpt->next_group++;
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/* Configure group mask for the mcode */
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cpt_configure_group(cpt, mcode->group, mcode->core_mask,
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AE_TYPES);
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/* Enable AE cores for the group mask */
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cpt_enable_cores(cpt, mcode->core_mask, AE_TYPES);
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} else {
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if (mcode->num_cores > cpt->max_se_cores) {
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dev_err(dev, "Requested for more cores than available SE cores\n");
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ret = -EINVAL;
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goto cpt_init_fail;
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}
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if (cpt->next_group >= CPT_MAX_CORE_GROUPS) {
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dev_err(dev, "Can't load, all eight microcode groups in use");
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return -ENFILE;
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}
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mcode->group = cpt->next_group;
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/* Covert requested cores to mask */
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mcode->core_mask = GENMASK(mcode->num_cores, 0);
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cpt_disable_cores(cpt, mcode->core_mask, SE_TYPES,
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mcode->group);
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/* Load microcode for SE engines */
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ret = cpt_load_microcode(cpt, mcode);
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if (ret) {
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dev_err(dev, "Microcode load Failed for %s\n",
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mcode->version);
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goto cpt_init_fail;
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}
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cpt->next_group++;
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/* Configure group mask for the mcode */
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cpt_configure_group(cpt, mcode->group, mcode->core_mask,
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SE_TYPES);
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/* Enable SE cores for the group mask */
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cpt_enable_cores(cpt, mcode->core_mask, SE_TYPES);
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}
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/* Enabled PF mailbox interrupts */
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cpt_enable_mbox_interrupts(cpt);
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cpt->flags |= CPT_FLAG_DEVICE_READY;
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return ret;
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cpt_init_fail:
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/* Enabled PF mailbox interrupts */
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cpt_enable_mbox_interrupts(cpt);
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return ret;
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}
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struct ucode_header {
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u8 version[CPT_UCODE_VERSION_SZ];
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u32 code_length;
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u32 data_length;
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u64 sram_address;
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};
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static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae)
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{
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const struct firmware *fw_entry;
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struct device *dev = &cpt->pdev->dev;
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struct ucode_header *ucode;
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struct microcode *mcode;
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int j, ret = 0;
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ret = request_firmware(&fw_entry, fw, dev);
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if (ret)
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return ret;
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ucode = (struct ucode_header *)fw_entry->data;
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mcode = &cpt->mcode[cpt->next_mc_idx];
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memcpy(mcode->version, (u8 *)fw_entry->data, CPT_UCODE_VERSION_SZ);
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mcode->code_size = ntohl(ucode->code_length) * 2;
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if (!mcode->code_size)
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return -EINVAL;
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mcode->is_ae = is_ae;
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mcode->core_mask = 0ULL;
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mcode->num_cores = is_ae ? 6 : 10;
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/* Allocate DMAable space */
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mcode->code = dma_zalloc_coherent(&cpt->pdev->dev, mcode->code_size,
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&mcode->phys_base, GFP_KERNEL);
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if (!mcode->code) {
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dev_err(dev, "Unable to allocate space for microcode");
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return -ENOMEM;
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}
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memcpy((void *)mcode->code, (void *)(fw_entry->data + sizeof(*ucode)),
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mcode->code_size);
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/* Byte swap 64-bit */
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for (j = 0; j < (mcode->code_size / 8); j++)
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((u64 *)mcode->code)[j] = cpu_to_be64(((u64 *)mcode->code)[j]);
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/* MC needs 16-bit swap */
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for (j = 0; j < (mcode->code_size / 2); j++)
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((u16 *)mcode->code)[j] = cpu_to_be16(((u16 *)mcode->code)[j]);
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dev_dbg(dev, "mcode->code_size = %u\n", mcode->code_size);
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dev_dbg(dev, "mcode->is_ae = %u\n", mcode->is_ae);
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dev_dbg(dev, "mcode->num_cores = %u\n", mcode->num_cores);
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dev_dbg(dev, "mcode->code = %llx\n", (u64)mcode->code);
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dev_dbg(dev, "mcode->phys_base = %llx\n", mcode->phys_base);
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ret = do_cpt_init(cpt, mcode);
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if (ret) {
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dev_err(dev, "do_cpt_init failed with ret: %d\n", ret);
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return ret;
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}
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dev_info(dev, "Microcode Loaded %s\n", mcode->version);
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mcode->is_mc_valid = 1;
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cpt->next_mc_idx++;
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release_firmware(fw_entry);
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return ret;
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}
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static int cpt_ucode_load(struct cpt_device *cpt)
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{
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int ret = 0;
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struct device *dev = &cpt->pdev->dev;
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ret = cpt_ucode_load_fw(cpt, "cpt8x-mc-ae.out", true);
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if (ret) {
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dev_err(dev, "ae:cpt_ucode_load failed with ret: %d\n", ret);
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return ret;
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}
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ret = cpt_ucode_load_fw(cpt, "cpt8x-mc-se.out", false);
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if (ret) {
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dev_err(dev, "se:cpt_ucode_load failed with ret: %d\n", ret);
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return ret;
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}
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return ret;
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}
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static irqreturn_t cpt_mbx0_intr_handler(int irq, void *cpt_irq)
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{
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struct cpt_device *cpt = (struct cpt_device *)cpt_irq;
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cpt_mbox_intr_handler(cpt, 0);
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return IRQ_HANDLED;
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}
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static void cpt_reset(struct cpt_device *cpt)
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{
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cpt_write_csr64(cpt->reg_base, CPTX_PF_RESET(0), 1);
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}
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static void cpt_find_max_enabled_cores(struct cpt_device *cpt)
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{
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union cptx_pf_constants pf_cnsts = {0};
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pf_cnsts.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_CONSTANTS(0));
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cpt->max_se_cores = pf_cnsts.s.se;
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cpt->max_ae_cores = pf_cnsts.s.ae;
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}
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static u32 cpt_check_bist_status(struct cpt_device *cpt)
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{
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union cptx_pf_bist_status bist_sts = {0};
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bist_sts.u = cpt_read_csr64(cpt->reg_base,
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CPTX_PF_BIST_STATUS(0));
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return bist_sts.u;
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}
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static u64 cpt_check_exe_bist_status(struct cpt_device *cpt)
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{
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union cptx_pf_exe_bist_status bist_sts = {0};
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bist_sts.u = cpt_read_csr64(cpt->reg_base,
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CPTX_PF_EXE_BIST_STATUS(0));
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return bist_sts.u;
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}
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static void cpt_disable_all_cores(struct cpt_device *cpt)
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{
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u32 grp, timeout = 100;
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struct device *dev = &cpt->pdev->dev;
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/* Disengage the cores from groups */
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for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) {
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cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0);
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udelay(CSR_DELAY);
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}
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grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));
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while (grp) {
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dev_err(dev, "Cores still busy");
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grp = cpt_read_csr64(cpt->reg_base,
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CPTX_PF_EXEC_BUSY(0));
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if (timeout--)
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break;
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udelay(CSR_DELAY);
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}
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/* Disable the cores */
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cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0);
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}
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/**
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* Ensure all cores are disengaged from all groups by
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* calling cpt_disable_all_cores() before calling this
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* function.
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*/
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static void cpt_unload_microcode(struct cpt_device *cpt)
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{
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u32 grp = 0, core;
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/* Free microcode bases and reset group masks */
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for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) {
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struct microcode *mcode = &cpt->mcode[grp];
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if (cpt->mcode[grp].code)
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dma_free_coherent(&cpt->pdev->dev, mcode->code_size,
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mcode->code, mcode->phys_base);
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mcode->code = NULL;
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}
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/* Clear UCODE_BASE registers for all engines */
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for (core = 0; core < CPT_MAX_TOTAL_CORES; core++)
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cpt_write_csr64(cpt->reg_base,
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CPTX_PF_ENGX_UCODE_BASE(0, core), 0ull);
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}
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static int cpt_device_init(struct cpt_device *cpt)
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{
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u64 bist;
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struct device *dev = &cpt->pdev->dev;
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/* Reset the PF when probed first */
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cpt_reset(cpt);
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mdelay(100);
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/*Check BIST status*/
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bist = (u64)cpt_check_bist_status(cpt);
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if (bist) {
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dev_err(dev, "RAM BIST failed with code 0x%llx", bist);
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return -ENODEV;
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}
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bist = cpt_check_exe_bist_status(cpt);
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if (bist) {
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dev_err(dev, "Engine BIST failed with code 0x%llx", bist);
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return -ENODEV;
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}
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/*Get CLK frequency*/
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/*Get max enabled cores */
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cpt_find_max_enabled_cores(cpt);
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/*Disable all cores*/
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cpt_disable_all_cores(cpt);
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/*Reset device parameters*/
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cpt->next_mc_idx = 0;
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cpt->next_group = 0;
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/* PF is ready */
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cpt->flags |= CPT_FLAG_DEVICE_READY;
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return 0;
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}
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static int cpt_register_interrupts(struct cpt_device *cpt)
|
|
{
|
|
int ret;
|
|
struct device *dev = &cpt->pdev->dev;
|
|
|
|
/* Enable MSI-X */
|
|
ret = pci_alloc_irq_vectors(cpt->pdev, CPT_PF_MSIX_VECTORS,
|
|
CPT_PF_MSIX_VECTORS, PCI_IRQ_MSIX);
|
|
if (ret < 0) {
|
|
dev_err(&cpt->pdev->dev, "Request for #%d msix vectors failed\n",
|
|
CPT_PF_MSIX_VECTORS);
|
|
return ret;
|
|
}
|
|
|
|
/* Register mailbox interrupt handlers */
|
|
ret = request_irq(pci_irq_vector(cpt->pdev, CPT_PF_INT_VEC_E_MBOXX(0)),
|
|
cpt_mbx0_intr_handler, 0, "CPT Mbox0", cpt);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
/* Enable mailbox interrupt */
|
|
cpt_enable_mbox_interrupts(cpt);
|
|
return 0;
|
|
|
|
fail:
|
|
dev_err(dev, "Request irq failed\n");
|
|
pci_disable_msix(cpt->pdev);
|
|
return ret;
|
|
}
|
|
|
|
static void cpt_unregister_interrupts(struct cpt_device *cpt)
|
|
{
|
|
free_irq(pci_irq_vector(cpt->pdev, CPT_PF_INT_VEC_E_MBOXX(0)), cpt);
|
|
pci_disable_msix(cpt->pdev);
|
|
}
|
|
|
|
static int cpt_sriov_init(struct cpt_device *cpt, int num_vfs)
|
|
{
|
|
int pos = 0;
|
|
int err;
|
|
u16 total_vf_cnt;
|
|
struct pci_dev *pdev = cpt->pdev;
|
|
|
|
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
|
|
if (!pos) {
|
|
dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
cpt->num_vf_en = num_vfs; /* User requested VFs */
|
|
pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
|
|
if (total_vf_cnt < cpt->num_vf_en)
|
|
cpt->num_vf_en = total_vf_cnt;
|
|
|
|
if (!total_vf_cnt)
|
|
return 0;
|
|
|
|
/*Enabled the available VFs */
|
|
err = pci_enable_sriov(pdev, cpt->num_vf_en);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
|
|
cpt->num_vf_en);
|
|
cpt->num_vf_en = 0;
|
|
return err;
|
|
}
|
|
|
|
/* TODO: Optionally enable static VQ priorities feature */
|
|
|
|
dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
|
|
cpt->num_vf_en);
|
|
|
|
cpt->flags |= CPT_FLAG_SRIOV_ENABLED;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpt_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct cpt_device *cpt;
|
|
int err;
|
|
|
|
if (num_vfs > 16 || num_vfs < 4) {
|
|
dev_warn(dev, "Invalid vf count %d, Resetting it to 4(default)\n",
|
|
num_vfs);
|
|
num_vfs = 4;
|
|
}
|
|
|
|
cpt = devm_kzalloc(dev, sizeof(*cpt), GFP_KERNEL);
|
|
if (!cpt)
|
|
return -ENOMEM;
|
|
|
|
pci_set_drvdata(pdev, cpt);
|
|
cpt->pdev = pdev;
|
|
err = pci_enable_device(pdev);
|
|
if (err) {
|
|
dev_err(dev, "Failed to enable PCI device\n");
|
|
pci_set_drvdata(pdev, NULL);
|
|
return err;
|
|
}
|
|
|
|
err = pci_request_regions(pdev, DRV_NAME);
|
|
if (err) {
|
|
dev_err(dev, "PCI request regions failed 0x%x\n", err);
|
|
goto cpt_err_disable_device;
|
|
}
|
|
|
|
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
|
|
if (err) {
|
|
dev_err(dev, "Unable to get usable DMA configuration\n");
|
|
goto cpt_err_release_regions;
|
|
}
|
|
|
|
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
|
|
if (err) {
|
|
dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
|
|
goto cpt_err_release_regions;
|
|
}
|
|
|
|
/* MAP PF's configuration registers */
|
|
cpt->reg_base = pcim_iomap(pdev, 0, 0);
|
|
if (!cpt->reg_base) {
|
|
dev_err(dev, "Cannot map config register space, aborting\n");
|
|
err = -ENOMEM;
|
|
goto cpt_err_release_regions;
|
|
}
|
|
|
|
/* CPT device HW initialization */
|
|
cpt_device_init(cpt);
|
|
|
|
/* Register interrupts */
|
|
err = cpt_register_interrupts(cpt);
|
|
if (err)
|
|
goto cpt_err_release_regions;
|
|
|
|
err = cpt_ucode_load(cpt);
|
|
if (err)
|
|
goto cpt_err_unregister_interrupts;
|
|
|
|
/* Configure SRIOV */
|
|
err = cpt_sriov_init(cpt, num_vfs);
|
|
if (err)
|
|
goto cpt_err_unregister_interrupts;
|
|
|
|
return 0;
|
|
|
|
cpt_err_unregister_interrupts:
|
|
cpt_unregister_interrupts(cpt);
|
|
cpt_err_release_regions:
|
|
pci_release_regions(pdev);
|
|
cpt_err_disable_device:
|
|
pci_disable_device(pdev);
|
|
pci_set_drvdata(pdev, NULL);
|
|
return err;
|
|
}
|
|
|
|
static void cpt_remove(struct pci_dev *pdev)
|
|
{
|
|
struct cpt_device *cpt = pci_get_drvdata(pdev);
|
|
|
|
/* Disengage SE and AE cores from all groups*/
|
|
cpt_disable_all_cores(cpt);
|
|
/* Unload microcodes */
|
|
cpt_unload_microcode(cpt);
|
|
cpt_unregister_interrupts(cpt);
|
|
pci_disable_sriov(pdev);
|
|
pci_release_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
pci_set_drvdata(pdev, NULL);
|
|
}
|
|
|
|
static void cpt_shutdown(struct pci_dev *pdev)
|
|
{
|
|
struct cpt_device *cpt = pci_get_drvdata(pdev);
|
|
|
|
if (!cpt)
|
|
return;
|
|
|
|
dev_info(&pdev->dev, "Shutdown device %x:%x.\n",
|
|
(u32)pdev->vendor, (u32)pdev->device);
|
|
|
|
cpt_unregister_interrupts(cpt);
|
|
pci_release_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
pci_set_drvdata(pdev, NULL);
|
|
}
|
|
|
|
/* Supported devices */
|
|
static const struct pci_device_id cpt_id_table[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_PF_DEVICE_ID) },
|
|
{ 0, } /* end of table */
|
|
};
|
|
|
|
static struct pci_driver cpt_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = cpt_id_table,
|
|
.probe = cpt_probe,
|
|
.remove = cpt_remove,
|
|
.shutdown = cpt_shutdown,
|
|
};
|
|
|
|
module_pci_driver(cpt_pci_driver);
|
|
|
|
MODULE_AUTHOR("George Cherian <george.cherian@cavium.com>");
|
|
MODULE_DESCRIPTION("Cavium Thunder CPT Physical Function Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_VERSION(DRV_VERSION);
|
|
MODULE_DEVICE_TABLE(pci, cpt_id_table);
|