![Andrew Donnellan](/assets/img/avatar_default.png)
Commit14a3ae34bf
("cxl: Prevent read/write to AFU config space while AFU not configured") introduced a rwsem to fix an invalid memory access that occurred when someone attempts to access the config space of an AFU on a vPHB whilst the AFU is deconfigured, such as during EEH recovery. It turns out that it's possible to run into a nested locking issue when EEH recovery fails and a full device hotplug is required. cxl_pci_error_detected() deconfigures the AFU, taking a writer lock on configured_rwsem. When EEH recovery fails, the EEH code calls pci_hp_remove_devices() to remove the device, which in turn calls cxl_remove() -> cxl_pci_remove_afu() -> pci_deconfigure_afu(), which tries to grab the writer lock that's already held. Standard rwsem semantics don't express what we really want to do here and don't allow for nested locking. Fix this by replacing the rwsem with an atomic_t which we can control more finely. Allow the AFU to be locked multiple times so long as there are no readers. Fixes:14a3ae34bf
("cxl: Prevent read/write to AFU config space while AFU not configured") Cc: stable@vger.kernel.org # v4.9+ Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
322 lines
7.4 KiB
C
322 lines
7.4 KiB
C
/*
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* Copyright 2014 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/pci.h>
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#include <misc/cxl.h>
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#include <asm/pnv-pci.h>
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#include "cxl.h"
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static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
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{
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if (dma_mask < DMA_BIT_MASK(64)) {
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pr_info("%s only 64bit DMA supported on CXL", __func__);
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return -EIO;
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}
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*(pdev->dev.dma_mask) = dma_mask;
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return 0;
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}
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static int cxl_pci_probe_mode(struct pci_bus *bus)
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{
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return PCI_PROBE_NORMAL;
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}
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static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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return -ENODEV;
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}
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static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
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{
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/*
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* MSI should never be set but need still need to provide this call
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* back.
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*/
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}
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static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
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{
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struct pci_controller *phb;
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struct cxl_afu *afu;
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phb = pci_bus_to_host(dev->bus);
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afu = (struct cxl_afu *)phb->private_data;
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if (!cxl_ops->link_ok(afu->adapter, afu)) {
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dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__);
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return false;
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}
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set_dma_ops(&dev->dev, &dma_direct_ops);
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set_dma_offset(&dev->dev, PAGE_OFFSET);
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return _cxl_pci_associate_default_context(dev, afu);
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}
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static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
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unsigned long type)
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{
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return 1;
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}
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static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
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{
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/* Should we do an AFU reset here ? */
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}
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static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
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{
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return (bus << 8) + devfn;
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}
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static inline struct cxl_afu *pci_bus_to_afu(struct pci_bus *bus)
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{
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struct pci_controller *phb = bus ? pci_bus_to_host(bus) : NULL;
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return phb ? phb->private_data : NULL;
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}
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static void cxl_afu_configured_put(struct cxl_afu *afu)
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{
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atomic_dec_if_positive(&afu->configured_state);
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}
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static bool cxl_afu_configured_get(struct cxl_afu *afu)
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{
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return atomic_inc_unless_negative(&afu->configured_state);
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}
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static inline int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
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struct cxl_afu *afu, int *_record)
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{
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int record;
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record = cxl_pcie_cfg_record(bus->number, devfn);
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if (record > afu->crs_num)
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return PCIBIOS_DEVICE_NOT_FOUND;
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*_record = record;
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return 0;
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}
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static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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int rc, record;
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struct cxl_afu *afu;
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u8 val8;
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u16 val16;
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u32 val32;
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afu = pci_bus_to_afu(bus);
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/* Grab a reader lock on afu. */
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if (afu == NULL || !cxl_afu_configured_get(afu))
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return PCIBIOS_DEVICE_NOT_FOUND;
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rc = cxl_pcie_config_info(bus, devfn, afu, &record);
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if (rc)
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goto out;
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switch (len) {
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case 1:
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rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8);
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*val = val8;
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break;
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case 2:
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rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16);
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*val = val16;
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break;
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case 4:
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rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32);
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*val = val32;
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break;
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default:
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WARN_ON(1);
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}
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out:
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cxl_afu_configured_put(afu);
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return rc ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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int rc, record;
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struct cxl_afu *afu;
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afu = pci_bus_to_afu(bus);
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/* Grab a reader lock on afu. */
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if (afu == NULL || !cxl_afu_configured_get(afu))
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return PCIBIOS_DEVICE_NOT_FOUND;
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rc = cxl_pcie_config_info(bus, devfn, afu, &record);
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if (rc)
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goto out;
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switch (len) {
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case 1:
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rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff);
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break;
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case 2:
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rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff);
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break;
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case 4:
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rc = cxl_ops->afu_cr_write32(afu, record, offset, val);
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break;
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default:
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WARN_ON(1);
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}
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out:
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cxl_afu_configured_put(afu);
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return rc ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops cxl_pcie_pci_ops =
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{
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.read = cxl_pcie_read_config,
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.write = cxl_pcie_write_config,
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};
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static struct pci_controller_ops cxl_pci_controller_ops =
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{
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.probe_mode = cxl_pci_probe_mode,
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.enable_device_hook = cxl_pci_enable_device_hook,
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.disable_device = _cxl_pci_disable_device,
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.release_device = _cxl_pci_disable_device,
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.window_alignment = cxl_pci_window_alignment,
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.reset_secondary_bus = cxl_pci_reset_secondary_bus,
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.setup_msi_irqs = cxl_setup_msi_irqs,
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.teardown_msi_irqs = cxl_teardown_msi_irqs,
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.dma_set_mask = cxl_dma_set_mask,
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};
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int cxl_pci_vphb_add(struct cxl_afu *afu)
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{
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struct pci_controller *phb;
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struct device_node *vphb_dn;
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struct device *parent;
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/*
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* If there are no AFU configuration records we won't have anything to
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* expose under the vPHB, so skip creating one, returning success since
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* this is still a valid case. This will also opt us out of EEH
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* handling since we won't have anything special to do if there are no
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* kernel drivers attached to the vPHB, and EEH handling is not yet
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* supported in the peer model.
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*/
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if (!afu->crs_num)
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return 0;
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/* The parent device is the adapter. Reuse the device node of
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* the adapter.
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* We don't seem to care what device node is used for the vPHB,
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* but tools such as lsvpd walk up the device parents looking
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* for a valid location code, so we might as well show devices
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* attached to the adapter as being located on that adapter.
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*/
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parent = afu->adapter->dev.parent;
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vphb_dn = parent->of_node;
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/* Alloc and setup PHB data structure */
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phb = pcibios_alloc_controller(vphb_dn);
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if (!phb)
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return -ENODEV;
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/* Setup parent in sysfs */
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phb->parent = parent;
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/* Setup the PHB using arch provided callback */
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phb->ops = &cxl_pcie_pci_ops;
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phb->cfg_addr = NULL;
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phb->cfg_data = NULL;
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phb->private_data = afu;
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phb->controller_ops = cxl_pci_controller_ops;
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/* Scan the bus */
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pcibios_scan_phb(phb);
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if (phb->bus == NULL)
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return -ENXIO;
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/* Set release hook on root bus */
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pci_set_host_bridge_release(to_pci_host_bridge(phb->bus->bridge),
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pcibios_free_controller_deferred,
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(void *) phb);
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/* Claim resources. This might need some rework as well depending
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* whether we are doing probe-only or not, like assigning unassigned
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* resources etc...
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*/
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pcibios_claim_one_bus(phb->bus);
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/* Add probed PCI devices to the device model */
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pci_bus_add_devices(phb->bus);
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afu->phb = phb;
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return 0;
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}
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void cxl_pci_vphb_remove(struct cxl_afu *afu)
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{
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struct pci_controller *phb;
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/* If there is no configuration record we won't have one of these */
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if (!afu || !afu->phb)
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return;
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phb = afu->phb;
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afu->phb = NULL;
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pci_remove_root_bus(phb->bus);
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/*
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* We don't free phb here - that's handled by
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* pcibios_free_controller_deferred()
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*/
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}
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static bool _cxl_pci_is_vphb_device(struct pci_controller *phb)
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{
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return (phb->ops == &cxl_pcie_pci_ops);
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}
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bool cxl_pci_is_vphb_device(struct pci_dev *dev)
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{
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struct pci_controller *phb;
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phb = pci_bus_to_host(dev->bus);
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return _cxl_pci_is_vphb_device(phb);
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}
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struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
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{
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struct pci_controller *phb;
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phb = pci_bus_to_host(dev->bus);
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if (_cxl_pci_is_vphb_device(phb))
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return (struct cxl_afu *)phb->private_data;
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if (pnv_pci_on_cxl_phb(dev))
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return pnv_cxl_phb_to_afu(phb);
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return ERR_PTR(-ENODEV);
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}
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EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
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unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
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{
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return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
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}
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EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);
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