a2eb0fc07f
Since the newer HW sports two interrupts causes we cannot just simply acknowledge the interrupts directly in the quick handler and store the cause in the member variable, as the cause will be overridden upon next interrupt while the interrupt thread was not yet scheduled handling the previous interrupt. The simple fix is to disable interrupts in quick handler and acknowledge and enabled them in the interrupt thread. Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
/*
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*
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* Intel Management Engine Interface (Intel MEI) Linux driver
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* Copyright (c) 2003-2012, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef _MEI_INTERFACE_H_
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#define _MEI_INTERFACE_H_
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#include <linux/irqreturn.h>
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#include <linux/pci.h>
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#include <linux/mei.h>
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#include "mei_dev.h"
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#include "client.h"
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/*
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* mei_cfg - mei device configuration
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*
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* @fw_status: FW status
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* @quirk_probe: device exclusion quirk
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*/
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struct mei_cfg {
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const struct mei_fw_status fw_status;
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bool (*quirk_probe)(struct pci_dev *pdev);
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};
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#define MEI_PCI_DEVICE(dev, cfg) \
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.vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
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.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
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.driver_data = (kernel_ulong_t)&(cfg)
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#define MEI_ME_RPM_TIMEOUT 500 /* ms */
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/**
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* struct mei_me_hw - me hw specific data
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*
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* @cfg: per device generation config and ops
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* @mem_addr: io memory address
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* @pg_state: power gating state
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* @d0i3_supported: di03 support
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*/
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struct mei_me_hw {
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const struct mei_cfg *cfg;
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void __iomem *mem_addr;
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enum mei_pg_state pg_state;
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bool d0i3_supported;
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};
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#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
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extern const struct mei_cfg mei_me_legacy_cfg;
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extern const struct mei_cfg mei_me_ich_cfg;
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extern const struct mei_cfg mei_me_pch_cfg;
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extern const struct mei_cfg mei_me_pch_cpt_pbg_cfg;
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extern const struct mei_cfg mei_me_pch8_cfg;
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extern const struct mei_cfg mei_me_pch8_sps_cfg;
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struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
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const struct mei_cfg *cfg);
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int mei_me_pg_enter_sync(struct mei_device *dev);
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int mei_me_pg_exit_sync(struct mei_device *dev);
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irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
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irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
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#endif /* _MEI_INTERFACE_H_ */
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