![Bhumika Goyal](/assets/img/avatar_default.png)
Declare uart_ops structures as const as they are only stored in the ops field of an uart_port structure. This field is of type const, so uart_ops structures having this property can be made const too. File size details before and after patching. First line of every .o file shows the file size before patching and second line shows the size after patching. text data bss dec hex filename 2977 456 64 3497 da9 drivers/tty/serial/amba-pl010.o 3169 272 64 3505 db1 drivers/tty/serial/amba-pl010.o 3109 456 0 3565 ded drivers/tty/serial/efm32-uart.o 3301 272 0 3573 df5 drivers/tty/serial/efm32-uart.o 10668 753 1 11422 2c9e drivers/tty/serial/icom.o 10860 561 1 11422 2c9e drivers/tty/serial/icom.o 23904 408 8 24320 5f00 drivers/tty/serial/ioc3_serial.o 24088 224 8 24320 5f00 drivers/tty/serial/ioc3_serial.o 10516 560 4 11080 2b48 drivers/tty/serial/ioc4_serial.o 10709 368 4 11081 2b49 drivers/tty/serial/ioc4_serial.o 7853 648 1216 9717 25f5 drivers/tty/serial/mpsc.o 8037 456 1216 9709 25ed drivers/tty/serial/mpsc.o 10248 456 0 10704 29d0 drivers/tty/serial/omap-serial.o 10440 272 0 10712 29d8 drivers/tty/serial/omap-serial.o 8122 532 1984 10638 298e drivers/tty/serial/pmac_zilog.o 8306 340 1984 10630 2986 drivers/tty/serial/pmac_zilog.o 3808 456 0 4264 10a8 drivers/tty/serial/pxa.o 4000 264 0 4264 10a8 drivers/tty/serial/pxa.o 21781 3864 0 25645 642d drivers/tty/serial/serial-tegra.o 22037 3608 0 25645 642d drivers/tty/serial/serial-tegra.o 2481 456 96 3033 bd9 drivers/tty/serial/sprd_serial.o 2673 272 96 3041 be1 drivers/tty/serial/sprd_serial.o 5534 300 512 6346 18ca drivers/tty/serial/vr41xx_siu.o 5630 204 512 6346 18ca drivers/tty/serial/vr41xx_siu.o 6730 1576 128 8434 20f2 drivers/tty/serial/vt8500_serial.o 6986 1320 128 8434 20f2 drivers/tty/serial/vt8500_serial.o Cross compiled for mips architecture. 3005 488 0 3493 da5 drivers/tty/serial/pnx8xxx_uart.o 3189 304 0 3493 da5 drivers/tty/serial/pnx8xxx_uart.o 4272 196 1056 5524 1594 drivers/tty/serial/dz.o 4368 100 1056 5524 1594 drivers/tty/serial/dz.o 6551 144 16 6711 1a37 drivers/tty/serial/ip22zilog.o 6647 48 16 6711 1a37 drivers/tty/serial/ip22zilog.o 9612 428 1520 11560 2d28 drivers/tty/serial/serial_txx9.o 9708 332 1520 11560 2d28 drivers/tty/serial/serial_txx9.o 4156 296 16 4468 1174 drivers/tty/serial/ar933x_uart.o 4252 200 16 4468 1174 drivers/tty/serial/ar933x_uart.o Cross compiled for arm archiecture. 11716 1780 44 13540 34e4 drivers/tty/serial/sirfsoc_uart.o 11808 1688 44 13540 34e4 drivers/tty/serial/sirfsoc_uart.o 13352 596 56 14004 36b4 drivers/tty/serial/amba-pl011.o 13444 504 56 14004 36b4 drivers/tty/serial/amba-pl011.o Cross compiled for sparc architecture. 4664 528 32 5224 1468 drivers/tty/serial/sunhv.o 4848 344 32 5224 1468 drivers/tty/serial/sunhv.o 8080 332 28 8440 20f8 drivers/tty/serial/sunzilog.o 8184 228 28 8440 20f8 drivers/tty/serial/sunzilog.o Cross compiled for ia64 architecture. 10226 549 472 11247 2bef drivers/tty/serial/sn_console.o 10414 365 472 11251 2bf3 drivers/tty/serial/sn_console.o The files drivers/tty/serial/zs.o, drivers/tty/serial/lpc32xx_hs.o and drivers/tty/serial/lantiq.o did not compile. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
844 lines
20 KiB
C
844 lines
20 KiB
C
/*
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* Driver for AMBA serial ports
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* Copyright 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This is a generic driver for ARM AMBA-type serial ports. They
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* have a lot of 16550-like features, but are not register compatible.
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* Note that although they do have CTS, DCD and DSR inputs, they do
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* not have an RI input, nor do they have DTR or RTS outputs. If
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* required, these have to be supplied via some other means (eg, GPIO)
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* and hooked into this driver.
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*/
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#if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#define UART_NR 8
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#define SERIAL_AMBA_MAJOR 204
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#define SERIAL_AMBA_MINOR 16
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#define SERIAL_AMBA_NR UART_NR
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#define AMBA_ISR_PASS_LIMIT 256
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#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
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#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
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#define UART_DUMMY_RSR_RX 256
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#define UART_PORT_SIZE 64
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/*
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* We wrap our port structure around the generic uart_port.
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*/
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struct uart_amba_port {
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struct uart_port port;
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struct clk *clk;
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struct amba_device *dev;
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struct amba_pl010_data *data;
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unsigned int old_status;
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};
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static void pl010_stop_tx(struct uart_port *port)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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unsigned int cr;
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cr = readb(uap->port.membase + UART010_CR);
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cr &= ~UART010_CR_TIE;
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writel(cr, uap->port.membase + UART010_CR);
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}
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static void pl010_start_tx(struct uart_port *port)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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unsigned int cr;
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cr = readb(uap->port.membase + UART010_CR);
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cr |= UART010_CR_TIE;
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writel(cr, uap->port.membase + UART010_CR);
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}
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static void pl010_stop_rx(struct uart_port *port)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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unsigned int cr;
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cr = readb(uap->port.membase + UART010_CR);
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cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
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writel(cr, uap->port.membase + UART010_CR);
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}
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static void pl010_disable_ms(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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unsigned int cr;
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cr = readb(uap->port.membase + UART010_CR);
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cr &= ~UART010_CR_MSIE;
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writel(cr, uap->port.membase + UART010_CR);
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}
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static void pl010_enable_ms(struct uart_port *port)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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unsigned int cr;
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cr = readb(uap->port.membase + UART010_CR);
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cr |= UART010_CR_MSIE;
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writel(cr, uap->port.membase + UART010_CR);
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}
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static void pl010_rx_chars(struct uart_amba_port *uap)
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{
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unsigned int status, ch, flag, rsr, max_count = 256;
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status = readb(uap->port.membase + UART01x_FR);
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while (UART_RX_DATA(status) && max_count--) {
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ch = readb(uap->port.membase + UART01x_DR);
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flag = TTY_NORMAL;
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uap->port.icount.rx++;
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/*
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* Note that the error handling code is
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* out of the main execution path
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*/
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rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
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if (unlikely(rsr & UART01x_RSR_ANY)) {
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writel(0, uap->port.membase + UART01x_ECR);
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if (rsr & UART01x_RSR_BE) {
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rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
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uap->port.icount.brk++;
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if (uart_handle_break(&uap->port))
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goto ignore_char;
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} else if (rsr & UART01x_RSR_PE)
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uap->port.icount.parity++;
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else if (rsr & UART01x_RSR_FE)
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uap->port.icount.frame++;
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if (rsr & UART01x_RSR_OE)
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uap->port.icount.overrun++;
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rsr &= uap->port.read_status_mask;
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if (rsr & UART01x_RSR_BE)
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flag = TTY_BREAK;
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else if (rsr & UART01x_RSR_PE)
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flag = TTY_PARITY;
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else if (rsr & UART01x_RSR_FE)
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flag = TTY_FRAME;
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}
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if (uart_handle_sysrq_char(&uap->port, ch))
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goto ignore_char;
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uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
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ignore_char:
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status = readb(uap->port.membase + UART01x_FR);
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}
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spin_unlock(&uap->port.lock);
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tty_flip_buffer_push(&uap->port.state->port);
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spin_lock(&uap->port.lock);
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}
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static void pl010_tx_chars(struct uart_amba_port *uap)
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{
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struct circ_buf *xmit = &uap->port.state->xmit;
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int count;
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if (uap->port.x_char) {
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writel(uap->port.x_char, uap->port.membase + UART01x_DR);
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uap->port.icount.tx++;
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uap->port.x_char = 0;
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return;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
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pl010_stop_tx(&uap->port);
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return;
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}
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count = uap->port.fifosize >> 1;
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do {
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writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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uap->port.icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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} while (--count > 0);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&uap->port);
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if (uart_circ_empty(xmit))
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pl010_stop_tx(&uap->port);
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}
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static void pl010_modem_status(struct uart_amba_port *uap)
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{
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unsigned int status, delta;
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writel(0, uap->port.membase + UART010_ICR);
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status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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delta = status ^ uap->old_status;
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uap->old_status = status;
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if (!delta)
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return;
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if (delta & UART01x_FR_DCD)
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uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
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if (delta & UART01x_FR_DSR)
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uap->port.icount.dsr++;
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if (delta & UART01x_FR_CTS)
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uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
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wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
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}
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static irqreturn_t pl010_int(int irq, void *dev_id)
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{
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struct uart_amba_port *uap = dev_id;
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unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
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int handled = 0;
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spin_lock(&uap->port.lock);
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status = readb(uap->port.membase + UART010_IIR);
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if (status) {
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do {
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if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
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pl010_rx_chars(uap);
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if (status & UART010_IIR_MIS)
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pl010_modem_status(uap);
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if (status & UART010_IIR_TIS)
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pl010_tx_chars(uap);
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if (pass_counter-- == 0)
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break;
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status = readb(uap->port.membase + UART010_IIR);
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} while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
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UART010_IIR_TIS));
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handled = 1;
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}
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spin_unlock(&uap->port.lock);
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return IRQ_RETVAL(handled);
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}
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static unsigned int pl010_tx_empty(struct uart_port *port)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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unsigned int status = readb(uap->port.membase + UART01x_FR);
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return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
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}
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static unsigned int pl010_get_mctrl(struct uart_port *port)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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unsigned int result = 0;
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unsigned int status;
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status = readb(uap->port.membase + UART01x_FR);
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if (status & UART01x_FR_DCD)
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result |= TIOCM_CAR;
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if (status & UART01x_FR_DSR)
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result |= TIOCM_DSR;
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if (status & UART01x_FR_CTS)
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result |= TIOCM_CTS;
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return result;
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}
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static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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if (uap->data)
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uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
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}
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static void pl010_break_ctl(struct uart_port *port, int break_state)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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unsigned long flags;
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unsigned int lcr_h;
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spin_lock_irqsave(&uap->port.lock, flags);
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lcr_h = readb(uap->port.membase + UART010_LCRH);
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if (break_state == -1)
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lcr_h |= UART01x_LCRH_BRK;
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else
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lcr_h &= ~UART01x_LCRH_BRK;
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writel(lcr_h, uap->port.membase + UART010_LCRH);
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spin_unlock_irqrestore(&uap->port.lock, flags);
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}
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static int pl010_startup(struct uart_port *port)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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int retval;
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/*
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* Try to enable the clock producer.
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*/
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retval = clk_prepare_enable(uap->clk);
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if (retval)
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goto out;
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uap->port.uartclk = clk_get_rate(uap->clk);
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/*
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* Allocate the IRQ
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*/
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retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
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if (retval)
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goto clk_dis;
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/*
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* initialise the old status of the modem signals
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*/
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uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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/*
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* Finally, enable interrupts
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*/
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writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
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uap->port.membase + UART010_CR);
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return 0;
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clk_dis:
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clk_disable_unprepare(uap->clk);
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out:
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return retval;
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}
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static void pl010_shutdown(struct uart_port *port)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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/*
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* Free the interrupt
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*/
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free_irq(uap->port.irq, uap);
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/*
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* disable all interrupts, disable the port
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*/
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writel(0, uap->port.membase + UART010_CR);
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/* disable break condition and fifos */
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writel(readb(uap->port.membase + UART010_LCRH) &
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~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
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uap->port.membase + UART010_LCRH);
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/*
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* Shut down the clock producer
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*/
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clk_disable_unprepare(uap->clk);
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}
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static void
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pl010_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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unsigned int lcr_h, old_cr;
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unsigned long flags;
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unsigned int baud, quot;
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/*
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* Ask the core to calculate the divisor for us.
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*/
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baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
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quot = uart_get_divisor(port, baud);
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switch (termios->c_cflag & CSIZE) {
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case CS5:
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lcr_h = UART01x_LCRH_WLEN_5;
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break;
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case CS6:
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lcr_h = UART01x_LCRH_WLEN_6;
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break;
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case CS7:
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lcr_h = UART01x_LCRH_WLEN_7;
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break;
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default: // CS8
|
|
lcr_h = UART01x_LCRH_WLEN_8;
|
|
break;
|
|
}
|
|
if (termios->c_cflag & CSTOPB)
|
|
lcr_h |= UART01x_LCRH_STP2;
|
|
if (termios->c_cflag & PARENB) {
|
|
lcr_h |= UART01x_LCRH_PEN;
|
|
if (!(termios->c_cflag & PARODD))
|
|
lcr_h |= UART01x_LCRH_EPS;
|
|
}
|
|
if (uap->port.fifosize > 1)
|
|
lcr_h |= UART01x_LCRH_FEN;
|
|
|
|
spin_lock_irqsave(&uap->port.lock, flags);
|
|
|
|
/*
|
|
* Update the per-port timeout.
|
|
*/
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
|
|
uap->port.read_status_mask = UART01x_RSR_OE;
|
|
if (termios->c_iflag & INPCK)
|
|
uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
|
|
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
|
|
uap->port.read_status_mask |= UART01x_RSR_BE;
|
|
|
|
/*
|
|
* Characters to ignore
|
|
*/
|
|
uap->port.ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNPAR)
|
|
uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
|
|
if (termios->c_iflag & IGNBRK) {
|
|
uap->port.ignore_status_mask |= UART01x_RSR_BE;
|
|
/*
|
|
* If we're ignoring parity and break indicators,
|
|
* ignore overruns too (for real raw support).
|
|
*/
|
|
if (termios->c_iflag & IGNPAR)
|
|
uap->port.ignore_status_mask |= UART01x_RSR_OE;
|
|
}
|
|
|
|
/*
|
|
* Ignore all characters if CREAD is not set.
|
|
*/
|
|
if ((termios->c_cflag & CREAD) == 0)
|
|
uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
|
|
|
|
/* first, disable everything */
|
|
old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
|
|
|
|
if (UART_ENABLE_MS(port, termios->c_cflag))
|
|
old_cr |= UART010_CR_MSIE;
|
|
|
|
writel(0, uap->port.membase + UART010_CR);
|
|
|
|
/* Set baud rate */
|
|
quot -= 1;
|
|
writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
|
|
writel(quot & 0xff, uap->port.membase + UART010_LCRL);
|
|
|
|
/*
|
|
* ----------v----------v----------v----------v-----
|
|
* NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
|
|
* ----------^----------^----------^----------^-----
|
|
*/
|
|
writel(lcr_h, uap->port.membase + UART010_LCRH);
|
|
writel(old_cr, uap->port.membase + UART010_CR);
|
|
|
|
spin_unlock_irqrestore(&uap->port.lock, flags);
|
|
}
|
|
|
|
static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios)
|
|
{
|
|
if (termios->c_line == N_PPS) {
|
|
port->flags |= UPF_HARDPPS_CD;
|
|
spin_lock_irq(&port->lock);
|
|
pl010_enable_ms(port);
|
|
spin_unlock_irq(&port->lock);
|
|
} else {
|
|
port->flags &= ~UPF_HARDPPS_CD;
|
|
if (!UART_ENABLE_MS(port, termios->c_cflag)) {
|
|
spin_lock_irq(&port->lock);
|
|
pl010_disable_ms(port);
|
|
spin_unlock_irq(&port->lock);
|
|
}
|
|
}
|
|
}
|
|
|
|
static const char *pl010_type(struct uart_port *port)
|
|
{
|
|
return port->type == PORT_AMBA ? "AMBA" : NULL;
|
|
}
|
|
|
|
/*
|
|
* Release the memory region(s) being used by 'port'
|
|
*/
|
|
static void pl010_release_port(struct uart_port *port)
|
|
{
|
|
release_mem_region(port->mapbase, UART_PORT_SIZE);
|
|
}
|
|
|
|
/*
|
|
* Request the memory region(s) being used by 'port'
|
|
*/
|
|
static int pl010_request_port(struct uart_port *port)
|
|
{
|
|
return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
|
|
!= NULL ? 0 : -EBUSY;
|
|
}
|
|
|
|
/*
|
|
* Configure/autoconfigure the port.
|
|
*/
|
|
static void pl010_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE) {
|
|
port->type = PORT_AMBA;
|
|
pl010_request_port(port);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* verify the new serial_struct (for TIOCSSERIAL).
|
|
*/
|
|
static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
{
|
|
int ret = 0;
|
|
if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
|
|
ret = -EINVAL;
|
|
if (ser->irq < 0 || ser->irq >= nr_irqs)
|
|
ret = -EINVAL;
|
|
if (ser->baud_base < 9600)
|
|
ret = -EINVAL;
|
|
return ret;
|
|
}
|
|
|
|
static const struct uart_ops amba_pl010_pops = {
|
|
.tx_empty = pl010_tx_empty,
|
|
.set_mctrl = pl010_set_mctrl,
|
|
.get_mctrl = pl010_get_mctrl,
|
|
.stop_tx = pl010_stop_tx,
|
|
.start_tx = pl010_start_tx,
|
|
.stop_rx = pl010_stop_rx,
|
|
.enable_ms = pl010_enable_ms,
|
|
.break_ctl = pl010_break_ctl,
|
|
.startup = pl010_startup,
|
|
.shutdown = pl010_shutdown,
|
|
.set_termios = pl010_set_termios,
|
|
.set_ldisc = pl010_set_ldisc,
|
|
.type = pl010_type,
|
|
.release_port = pl010_release_port,
|
|
.request_port = pl010_request_port,
|
|
.config_port = pl010_config_port,
|
|
.verify_port = pl010_verify_port,
|
|
};
|
|
|
|
static struct uart_amba_port *amba_ports[UART_NR];
|
|
|
|
#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
|
|
|
|
static void pl010_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
struct uart_amba_port *uap =
|
|
container_of(port, struct uart_amba_port, port);
|
|
unsigned int status;
|
|
|
|
do {
|
|
status = readb(uap->port.membase + UART01x_FR);
|
|
barrier();
|
|
} while (!UART_TX_READY(status));
|
|
writel(ch, uap->port.membase + UART01x_DR);
|
|
}
|
|
|
|
static void
|
|
pl010_console_write(struct console *co, const char *s, unsigned int count)
|
|
{
|
|
struct uart_amba_port *uap = amba_ports[co->index];
|
|
unsigned int status, old_cr;
|
|
|
|
clk_enable(uap->clk);
|
|
|
|
/*
|
|
* First save the CR then disable the interrupts
|
|
*/
|
|
old_cr = readb(uap->port.membase + UART010_CR);
|
|
writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
|
|
|
|
uart_console_write(&uap->port, s, count, pl010_console_putchar);
|
|
|
|
/*
|
|
* Finally, wait for transmitter to become empty
|
|
* and restore the TCR
|
|
*/
|
|
do {
|
|
status = readb(uap->port.membase + UART01x_FR);
|
|
barrier();
|
|
} while (status & UART01x_FR_BUSY);
|
|
writel(old_cr, uap->port.membase + UART010_CR);
|
|
|
|
clk_disable(uap->clk);
|
|
}
|
|
|
|
static void __init
|
|
pl010_console_get_options(struct uart_amba_port *uap, int *baud,
|
|
int *parity, int *bits)
|
|
{
|
|
if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
|
|
unsigned int lcr_h, quot;
|
|
lcr_h = readb(uap->port.membase + UART010_LCRH);
|
|
|
|
*parity = 'n';
|
|
if (lcr_h & UART01x_LCRH_PEN) {
|
|
if (lcr_h & UART01x_LCRH_EPS)
|
|
*parity = 'e';
|
|
else
|
|
*parity = 'o';
|
|
}
|
|
|
|
if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
|
|
*bits = 7;
|
|
else
|
|
*bits = 8;
|
|
|
|
quot = readb(uap->port.membase + UART010_LCRL) |
|
|
readb(uap->port.membase + UART010_LCRM) << 8;
|
|
*baud = uap->port.uartclk / (16 * (quot + 1));
|
|
}
|
|
}
|
|
|
|
static int __init pl010_console_setup(struct console *co, char *options)
|
|
{
|
|
struct uart_amba_port *uap;
|
|
int baud = 38400;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
int ret;
|
|
|
|
/*
|
|
* Check whether an invalid uart number has been specified, and
|
|
* if so, search for the first available port that does have
|
|
* console support.
|
|
*/
|
|
if (co->index >= UART_NR)
|
|
co->index = 0;
|
|
uap = amba_ports[co->index];
|
|
if (!uap)
|
|
return -ENODEV;
|
|
|
|
ret = clk_prepare(uap->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
uap->port.uartclk = clk_get_rate(uap->clk);
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
else
|
|
pl010_console_get_options(uap, &baud, &parity, &bits);
|
|
|
|
return uart_set_options(&uap->port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver amba_reg;
|
|
static struct console amba_console = {
|
|
.name = "ttyAM",
|
|
.write = pl010_console_write,
|
|
.device = uart_console_device,
|
|
.setup = pl010_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &amba_reg,
|
|
};
|
|
|
|
#define AMBA_CONSOLE &amba_console
|
|
#else
|
|
#define AMBA_CONSOLE NULL
|
|
#endif
|
|
|
|
static struct uart_driver amba_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "ttyAM",
|
|
.dev_name = "ttyAM",
|
|
.major = SERIAL_AMBA_MAJOR,
|
|
.minor = SERIAL_AMBA_MINOR,
|
|
.nr = UART_NR,
|
|
.cons = AMBA_CONSOLE,
|
|
};
|
|
|
|
static int pl010_probe(struct amba_device *dev, const struct amba_id *id)
|
|
{
|
|
struct uart_amba_port *uap;
|
|
void __iomem *base;
|
|
int i, ret;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
|
|
if (amba_ports[i] == NULL)
|
|
break;
|
|
|
|
if (i == ARRAY_SIZE(amba_ports))
|
|
return -EBUSY;
|
|
|
|
uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
|
|
GFP_KERNEL);
|
|
if (!uap)
|
|
return -ENOMEM;
|
|
|
|
base = devm_ioremap(&dev->dev, dev->res.start,
|
|
resource_size(&dev->res));
|
|
if (!base)
|
|
return -ENOMEM;
|
|
|
|
uap->clk = devm_clk_get(&dev->dev, NULL);
|
|
if (IS_ERR(uap->clk))
|
|
return PTR_ERR(uap->clk);
|
|
|
|
uap->port.dev = &dev->dev;
|
|
uap->port.mapbase = dev->res.start;
|
|
uap->port.membase = base;
|
|
uap->port.iotype = UPIO_MEM;
|
|
uap->port.irq = dev->irq[0];
|
|
uap->port.fifosize = 16;
|
|
uap->port.ops = &amba_pl010_pops;
|
|
uap->port.flags = UPF_BOOT_AUTOCONF;
|
|
uap->port.line = i;
|
|
uap->dev = dev;
|
|
uap->data = dev_get_platdata(&dev->dev);
|
|
|
|
amba_ports[i] = uap;
|
|
|
|
amba_set_drvdata(dev, uap);
|
|
ret = uart_add_one_port(&amba_reg, &uap->port);
|
|
if (ret)
|
|
amba_ports[i] = NULL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int pl010_remove(struct amba_device *dev)
|
|
{
|
|
struct uart_amba_port *uap = amba_get_drvdata(dev);
|
|
int i;
|
|
|
|
uart_remove_one_port(&amba_reg, &uap->port);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
|
|
if (amba_ports[i] == uap)
|
|
amba_ports[i] = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int pl010_suspend(struct device *dev)
|
|
{
|
|
struct uart_amba_port *uap = dev_get_drvdata(dev);
|
|
|
|
if (uap)
|
|
uart_suspend_port(&amba_reg, &uap->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pl010_resume(struct device *dev)
|
|
{
|
|
struct uart_amba_port *uap = dev_get_drvdata(dev);
|
|
|
|
if (uap)
|
|
uart_resume_port(&amba_reg, &uap->port);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume);
|
|
|
|
static struct amba_id pl010_ids[] = {
|
|
{
|
|
.id = 0x00041010,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{ 0, 0 },
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(amba, pl010_ids);
|
|
|
|
static struct amba_driver pl010_driver = {
|
|
.drv = {
|
|
.name = "uart-pl010",
|
|
.pm = &pl010_dev_pm_ops,
|
|
},
|
|
.id_table = pl010_ids,
|
|
.probe = pl010_probe,
|
|
.remove = pl010_remove,
|
|
};
|
|
|
|
static int __init pl010_init(void)
|
|
{
|
|
int ret;
|
|
|
|
printk(KERN_INFO "Serial: AMBA driver\n");
|
|
|
|
ret = uart_register_driver(&amba_reg);
|
|
if (ret == 0) {
|
|
ret = amba_driver_register(&pl010_driver);
|
|
if (ret)
|
|
uart_unregister_driver(&amba_reg);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void __exit pl010_exit(void)
|
|
{
|
|
amba_driver_unregister(&pl010_driver);
|
|
uart_unregister_driver(&amba_reg);
|
|
}
|
|
|
|
module_init(pl010_init);
|
|
module_exit(pl010_exit);
|
|
|
|
MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
|
|
MODULE_DESCRIPTION("ARM AMBA serial port driver");
|
|
MODULE_LICENSE("GPL");
|