![Bhumika Goyal](/assets/img/avatar_default.png)
Declare uart_ops structures as const as they are only stored in the ops field of an uart_port structure. This field is of type const, so uart_ops structures having this property can be made const too. File size details before and after patching. First line of every .o file shows the file size before patching and second line shows the size after patching. text data bss dec hex filename 2977 456 64 3497 da9 drivers/tty/serial/amba-pl010.o 3169 272 64 3505 db1 drivers/tty/serial/amba-pl010.o 3109 456 0 3565 ded drivers/tty/serial/efm32-uart.o 3301 272 0 3573 df5 drivers/tty/serial/efm32-uart.o 10668 753 1 11422 2c9e drivers/tty/serial/icom.o 10860 561 1 11422 2c9e drivers/tty/serial/icom.o 23904 408 8 24320 5f00 drivers/tty/serial/ioc3_serial.o 24088 224 8 24320 5f00 drivers/tty/serial/ioc3_serial.o 10516 560 4 11080 2b48 drivers/tty/serial/ioc4_serial.o 10709 368 4 11081 2b49 drivers/tty/serial/ioc4_serial.o 7853 648 1216 9717 25f5 drivers/tty/serial/mpsc.o 8037 456 1216 9709 25ed drivers/tty/serial/mpsc.o 10248 456 0 10704 29d0 drivers/tty/serial/omap-serial.o 10440 272 0 10712 29d8 drivers/tty/serial/omap-serial.o 8122 532 1984 10638 298e drivers/tty/serial/pmac_zilog.o 8306 340 1984 10630 2986 drivers/tty/serial/pmac_zilog.o 3808 456 0 4264 10a8 drivers/tty/serial/pxa.o 4000 264 0 4264 10a8 drivers/tty/serial/pxa.o 21781 3864 0 25645 642d drivers/tty/serial/serial-tegra.o 22037 3608 0 25645 642d drivers/tty/serial/serial-tegra.o 2481 456 96 3033 bd9 drivers/tty/serial/sprd_serial.o 2673 272 96 3041 be1 drivers/tty/serial/sprd_serial.o 5534 300 512 6346 18ca drivers/tty/serial/vr41xx_siu.o 5630 204 512 6346 18ca drivers/tty/serial/vr41xx_siu.o 6730 1576 128 8434 20f2 drivers/tty/serial/vt8500_serial.o 6986 1320 128 8434 20f2 drivers/tty/serial/vt8500_serial.o Cross compiled for mips architecture. 3005 488 0 3493 da5 drivers/tty/serial/pnx8xxx_uart.o 3189 304 0 3493 da5 drivers/tty/serial/pnx8xxx_uart.o 4272 196 1056 5524 1594 drivers/tty/serial/dz.o 4368 100 1056 5524 1594 drivers/tty/serial/dz.o 6551 144 16 6711 1a37 drivers/tty/serial/ip22zilog.o 6647 48 16 6711 1a37 drivers/tty/serial/ip22zilog.o 9612 428 1520 11560 2d28 drivers/tty/serial/serial_txx9.o 9708 332 1520 11560 2d28 drivers/tty/serial/serial_txx9.o 4156 296 16 4468 1174 drivers/tty/serial/ar933x_uart.o 4252 200 16 4468 1174 drivers/tty/serial/ar933x_uart.o Cross compiled for arm archiecture. 11716 1780 44 13540 34e4 drivers/tty/serial/sirfsoc_uart.o 11808 1688 44 13540 34e4 drivers/tty/serial/sirfsoc_uart.o 13352 596 56 14004 36b4 drivers/tty/serial/amba-pl011.o 13444 504 56 14004 36b4 drivers/tty/serial/amba-pl011.o Cross compiled for sparc architecture. 4664 528 32 5224 1468 drivers/tty/serial/sunhv.o 4848 344 32 5224 1468 drivers/tty/serial/sunhv.o 8080 332 28 8440 20f8 drivers/tty/serial/sunzilog.o 8184 228 28 8440 20f8 drivers/tty/serial/sunzilog.o Cross compiled for ia64 architecture. 10226 549 472 11247 2bef drivers/tty/serial/sn_console.o 10414 365 472 11251 2bf3 drivers/tty/serial/sn_console.o The files drivers/tty/serial/zs.o, drivers/tty/serial/lpc32xx_hs.o and drivers/tty/serial/lantiq.o did not compile. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
850 lines
21 KiB
C
850 lines
21 KiB
C
#if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/serial_core.h>
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#include <linux/tty_flip.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_data/efm32-uart.h>
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#define DRIVER_NAME "efm32-uart"
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#define DEV_NAME "ttyefm"
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#define UARTn_CTRL 0x00
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#define UARTn_CTRL_SYNC 0x0001
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#define UARTn_CTRL_TXBIL 0x1000
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#define UARTn_FRAME 0x04
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#define UARTn_FRAME_DATABITS__MASK 0x000f
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#define UARTn_FRAME_DATABITS(n) ((n) - 3)
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#define UARTn_FRAME_PARITY_NONE 0x0000
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#define UARTn_FRAME_PARITY_EVEN 0x0200
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#define UARTn_FRAME_PARITY_ODD 0x0300
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#define UARTn_FRAME_STOPBITS_HALF 0x0000
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#define UARTn_FRAME_STOPBITS_ONE 0x1000
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#define UARTn_FRAME_STOPBITS_TWO 0x3000
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#define UARTn_CMD 0x0c
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#define UARTn_CMD_RXEN 0x0001
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#define UARTn_CMD_RXDIS 0x0002
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#define UARTn_CMD_TXEN 0x0004
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#define UARTn_CMD_TXDIS 0x0008
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#define UARTn_STATUS 0x10
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#define UARTn_STATUS_TXENS 0x0002
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#define UARTn_STATUS_TXC 0x0020
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#define UARTn_STATUS_TXBL 0x0040
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#define UARTn_STATUS_RXDATAV 0x0080
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#define UARTn_CLKDIV 0x14
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#define UARTn_RXDATAX 0x18
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#define UARTn_RXDATAX_RXDATA__MASK 0x01ff
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#define UARTn_RXDATAX_PERR 0x4000
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#define UARTn_RXDATAX_FERR 0x8000
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/*
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* This is a software only flag used for ignore_status_mask and
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* read_status_mask! It's used for breaks that the hardware doesn't report
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* explicitly.
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*/
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#define SW_UARTn_RXDATAX_BERR 0x2000
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#define UARTn_TXDATA 0x34
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#define UARTn_IF 0x40
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#define UARTn_IF_TXC 0x0001
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#define UARTn_IF_TXBL 0x0002
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#define UARTn_IF_RXDATAV 0x0004
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#define UARTn_IF_RXOF 0x0010
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#define UARTn_IFS 0x44
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#define UARTn_IFC 0x48
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#define UARTn_IEN 0x4c
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#define UARTn_ROUTE 0x54
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#define UARTn_ROUTE_LOCATION__MASK 0x0700
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#define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
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#define UARTn_ROUTE_RXPEN 0x0001
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#define UARTn_ROUTE_TXPEN 0x0002
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struct efm32_uart_port {
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struct uart_port port;
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unsigned int txirq;
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struct clk *clk;
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struct efm32_uart_pdata pdata;
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};
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#define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
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#define efm_debug(efm_port, format, arg...) \
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dev_dbg(efm_port->port.dev, format, ##arg)
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static void efm32_uart_write32(struct efm32_uart_port *efm_port,
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u32 value, unsigned offset)
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{
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writel_relaxed(value, efm_port->port.membase + offset);
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}
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static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
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unsigned offset)
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{
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return readl_relaxed(efm_port->port.membase + offset);
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}
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static unsigned int efm32_uart_tx_empty(struct uart_port *port)
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{
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struct efm32_uart_port *efm_port = to_efm_port(port);
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u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
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if (status & UARTn_STATUS_TXC)
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return TIOCSER_TEMT;
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else
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return 0;
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}
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static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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/* sorry, neither handshaking lines nor loop functionallity */
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}
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static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
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{
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/* sorry, no handshaking lines available */
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return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
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}
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static void efm32_uart_stop_tx(struct uart_port *port)
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{
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struct efm32_uart_port *efm_port = to_efm_port(port);
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u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
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efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
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ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
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efm32_uart_write32(efm_port, ien, UARTn_IEN);
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}
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static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
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{
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struct uart_port *port = &efm_port->port;
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struct circ_buf *xmit = &port->state->xmit;
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while (efm32_uart_read32(efm_port, UARTn_STATUS) &
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UARTn_STATUS_TXBL) {
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if (port->x_char) {
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port->icount.tx++;
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efm32_uart_write32(efm_port, port->x_char,
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UARTn_TXDATA);
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port->x_char = 0;
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continue;
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}
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if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
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port->icount.tx++;
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efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
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UARTn_TXDATA);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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} else
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break;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (!port->x_char && uart_circ_empty(xmit) &&
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efm32_uart_read32(efm_port, UARTn_STATUS) &
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UARTn_STATUS_TXC)
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efm32_uart_stop_tx(port);
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}
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static void efm32_uart_start_tx(struct uart_port *port)
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{
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struct efm32_uart_port *efm_port = to_efm_port(port);
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u32 ien;
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efm32_uart_write32(efm_port,
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UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
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ien = efm32_uart_read32(efm_port, UARTn_IEN);
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efm32_uart_write32(efm_port,
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ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
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efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
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efm32_uart_tx_chars(efm_port);
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}
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static void efm32_uart_stop_rx(struct uart_port *port)
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{
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struct efm32_uart_port *efm_port = to_efm_port(port);
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efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
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}
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static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
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{
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/* not possible without fiddling with gpios */
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}
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static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
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{
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struct uart_port *port = &efm_port->port;
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while (efm32_uart_read32(efm_port, UARTn_STATUS) &
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UARTn_STATUS_RXDATAV) {
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u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
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int flag = 0;
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/*
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* This is a reserved bit and I only saw it read as 0. But to be
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* sure not to be confused too much by new devices adhere to the
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* warning in the reference manual that reserverd bits might
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* read as 1 in the future.
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*/
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rxdata &= ~SW_UARTn_RXDATAX_BERR;
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port->icount.rx++;
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if ((rxdata & UARTn_RXDATAX_FERR) &&
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!(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
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rxdata |= SW_UARTn_RXDATAX_BERR;
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port->icount.brk++;
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if (uart_handle_break(port))
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continue;
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} else if (rxdata & UARTn_RXDATAX_PERR)
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port->icount.parity++;
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else if (rxdata & UARTn_RXDATAX_FERR)
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port->icount.frame++;
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rxdata &= port->read_status_mask;
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if (rxdata & SW_UARTn_RXDATAX_BERR)
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flag = TTY_BREAK;
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else if (rxdata & UARTn_RXDATAX_PERR)
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flag = TTY_PARITY;
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else if (rxdata & UARTn_RXDATAX_FERR)
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flag = TTY_FRAME;
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else if (uart_handle_sysrq_char(port,
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rxdata & UARTn_RXDATAX_RXDATA__MASK))
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continue;
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if ((rxdata & port->ignore_status_mask) == 0)
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tty_insert_flip_char(&port->state->port,
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rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
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}
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}
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static irqreturn_t efm32_uart_rxirq(int irq, void *data)
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{
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struct efm32_uart_port *efm_port = data;
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u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
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int handled = IRQ_NONE;
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struct uart_port *port = &efm_port->port;
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struct tty_port *tport = &port->state->port;
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spin_lock(&port->lock);
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if (irqflag & UARTn_IF_RXDATAV) {
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efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
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efm32_uart_rx_chars(efm_port);
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handled = IRQ_HANDLED;
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}
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if (irqflag & UARTn_IF_RXOF) {
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efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
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port->icount.overrun++;
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tty_insert_flip_char(tport, 0, TTY_OVERRUN);
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handled = IRQ_HANDLED;
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}
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spin_unlock(&port->lock);
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tty_flip_buffer_push(tport);
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return handled;
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}
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static irqreturn_t efm32_uart_txirq(int irq, void *data)
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{
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struct efm32_uart_port *efm_port = data;
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u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
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/* TXBL doesn't need to be cleared */
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if (irqflag & UARTn_IF_TXC)
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efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
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if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
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efm32_uart_tx_chars(efm_port);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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static int efm32_uart_startup(struct uart_port *port)
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{
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struct efm32_uart_port *efm_port = to_efm_port(port);
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int ret;
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ret = clk_enable(efm_port->clk);
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if (ret) {
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efm_debug(efm_port, "failed to enable clk\n");
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goto err_clk_enable;
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}
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port->uartclk = clk_get_rate(efm_port->clk);
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/* Enable pins at configured location */
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efm32_uart_write32(efm_port,
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UARTn_ROUTE_LOCATION(efm_port->pdata.location) |
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UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
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UARTn_ROUTE);
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ret = request_irq(port->irq, efm32_uart_rxirq, 0,
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DRIVER_NAME, efm_port);
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if (ret) {
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efm_debug(efm_port, "failed to register rxirq\n");
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goto err_request_irq_rx;
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}
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/* disable all irqs */
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efm32_uart_write32(efm_port, 0, UARTn_IEN);
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ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
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DRIVER_NAME, efm_port);
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if (ret) {
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efm_debug(efm_port, "failed to register txirq\n");
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free_irq(port->irq, efm_port);
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err_request_irq_rx:
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clk_disable(efm_port->clk);
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} else {
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efm32_uart_write32(efm_port,
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UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
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efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
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}
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err_clk_enable:
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return ret;
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}
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static void efm32_uart_shutdown(struct uart_port *port)
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{
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struct efm32_uart_port *efm_port = to_efm_port(port);
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efm32_uart_write32(efm_port, 0, UARTn_IEN);
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free_irq(port->irq, efm_port);
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clk_disable(efm_port->clk);
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}
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static void efm32_uart_set_termios(struct uart_port *port,
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struct ktermios *new, struct ktermios *old)
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{
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struct efm32_uart_port *efm_port = to_efm_port(port);
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unsigned long flags;
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unsigned baud;
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u32 clkdiv;
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u32 frame = 0;
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/* no modem control lines */
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new->c_cflag &= ~(CRTSCTS | CMSPAR);
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baud = uart_get_baud_rate(port, new, old,
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DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
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DIV_ROUND_CLOSEST(port->uartclk, 16));
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switch (new->c_cflag & CSIZE) {
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case CS5:
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frame |= UARTn_FRAME_DATABITS(5);
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break;
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case CS6:
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frame |= UARTn_FRAME_DATABITS(6);
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break;
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case CS7:
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frame |= UARTn_FRAME_DATABITS(7);
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break;
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case CS8:
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frame |= UARTn_FRAME_DATABITS(8);
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break;
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}
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if (new->c_cflag & CSTOPB)
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/* the receiver only verifies the first stop bit */
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frame |= UARTn_FRAME_STOPBITS_TWO;
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else
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frame |= UARTn_FRAME_STOPBITS_ONE;
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if (new->c_cflag & PARENB) {
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if (new->c_cflag & PARODD)
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frame |= UARTn_FRAME_PARITY_ODD;
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else
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frame |= UARTn_FRAME_PARITY_EVEN;
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} else
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frame |= UARTn_FRAME_PARITY_NONE;
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/*
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* the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
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* port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
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*/
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clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
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spin_lock_irqsave(&port->lock, flags);
|
|
|
|
efm32_uart_write32(efm_port,
|
|
UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
|
|
|
|
port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
|
|
if (new->c_iflag & INPCK)
|
|
port->read_status_mask |=
|
|
UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
|
|
if (new->c_iflag & (IGNBRK | BRKINT | PARMRK))
|
|
port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
|
|
|
|
port->ignore_status_mask = 0;
|
|
if (new->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |=
|
|
UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
|
|
if (new->c_iflag & IGNBRK)
|
|
port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
|
|
|
|
uart_update_timeout(port, new->c_cflag, baud);
|
|
|
|
efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
|
|
efm32_uart_write32(efm_port, frame, UARTn_FRAME);
|
|
efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
|
|
|
|
efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
|
|
UARTn_CMD);
|
|
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
static const char *efm32_uart_type(struct uart_port *port)
|
|
{
|
|
return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
|
|
}
|
|
|
|
static void efm32_uart_release_port(struct uart_port *port)
|
|
{
|
|
struct efm32_uart_port *efm_port = to_efm_port(port);
|
|
|
|
clk_unprepare(efm_port->clk);
|
|
clk_put(efm_port->clk);
|
|
iounmap(port->membase);
|
|
}
|
|
|
|
static int efm32_uart_request_port(struct uart_port *port)
|
|
{
|
|
struct efm32_uart_port *efm_port = to_efm_port(port);
|
|
int ret;
|
|
|
|
port->membase = ioremap(port->mapbase, 60);
|
|
if (!efm_port->port.membase) {
|
|
ret = -ENOMEM;
|
|
efm_debug(efm_port, "failed to remap\n");
|
|
goto err_ioremap;
|
|
}
|
|
|
|
efm_port->clk = clk_get(port->dev, NULL);
|
|
if (IS_ERR(efm_port->clk)) {
|
|
ret = PTR_ERR(efm_port->clk);
|
|
efm_debug(efm_port, "failed to get clock\n");
|
|
goto err_clk_get;
|
|
}
|
|
|
|
ret = clk_prepare(efm_port->clk);
|
|
if (ret) {
|
|
clk_put(efm_port->clk);
|
|
err_clk_get:
|
|
|
|
iounmap(port->membase);
|
|
err_ioremap:
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void efm32_uart_config_port(struct uart_port *port, int type)
|
|
{
|
|
if (type & UART_CONFIG_TYPE &&
|
|
!efm32_uart_request_port(port))
|
|
port->type = PORT_EFMUART;
|
|
}
|
|
|
|
static int efm32_uart_verify_port(struct uart_port *port,
|
|
struct serial_struct *serinfo)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
|
|
ret = -EINVAL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct uart_ops efm32_uart_pops = {
|
|
.tx_empty = efm32_uart_tx_empty,
|
|
.set_mctrl = efm32_uart_set_mctrl,
|
|
.get_mctrl = efm32_uart_get_mctrl,
|
|
.stop_tx = efm32_uart_stop_tx,
|
|
.start_tx = efm32_uart_start_tx,
|
|
.stop_rx = efm32_uart_stop_rx,
|
|
.break_ctl = efm32_uart_break_ctl,
|
|
.startup = efm32_uart_startup,
|
|
.shutdown = efm32_uart_shutdown,
|
|
.set_termios = efm32_uart_set_termios,
|
|
.type = efm32_uart_type,
|
|
.release_port = efm32_uart_release_port,
|
|
.request_port = efm32_uart_request_port,
|
|
.config_port = efm32_uart_config_port,
|
|
.verify_port = efm32_uart_verify_port,
|
|
};
|
|
|
|
static struct efm32_uart_port *efm32_uart_ports[5];
|
|
|
|
#ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
|
|
static void efm32_uart_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
struct efm32_uart_port *efm_port = to_efm_port(port);
|
|
unsigned int timeout = 0x400;
|
|
u32 status;
|
|
|
|
while (1) {
|
|
status = efm32_uart_read32(efm_port, UARTn_STATUS);
|
|
|
|
if (status & UARTn_STATUS_TXBL)
|
|
break;
|
|
if (!timeout--)
|
|
return;
|
|
}
|
|
efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
|
|
}
|
|
|
|
static void efm32_uart_console_write(struct console *co, const char *s,
|
|
unsigned int count)
|
|
{
|
|
struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
|
|
u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
|
|
unsigned int timeout = 0x400;
|
|
|
|
if (!(status & UARTn_STATUS_TXENS))
|
|
efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
|
|
|
|
uart_console_write(&efm_port->port, s, count,
|
|
efm32_uart_console_putchar);
|
|
|
|
/* Wait for the transmitter to become empty */
|
|
while (1) {
|
|
u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
|
|
if (status & UARTn_STATUS_TXC)
|
|
break;
|
|
if (!timeout--)
|
|
break;
|
|
}
|
|
|
|
if (!(status & UARTn_STATUS_TXENS))
|
|
efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
|
|
}
|
|
|
|
static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
|
|
int *baud, int *parity, int *bits)
|
|
{
|
|
u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
|
|
u32 route, clkdiv, frame;
|
|
|
|
if (ctrl & UARTn_CTRL_SYNC)
|
|
/* not operating in async mode */
|
|
return;
|
|
|
|
route = efm32_uart_read32(efm_port, UARTn_ROUTE);
|
|
if (!(route & UARTn_ROUTE_TXPEN))
|
|
/* tx pin not routed */
|
|
return;
|
|
|
|
clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
|
|
|
|
*baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
|
|
16 * (4 + (clkdiv >> 6)));
|
|
|
|
frame = efm32_uart_read32(efm_port, UARTn_FRAME);
|
|
if (frame & UARTn_FRAME_PARITY_ODD)
|
|
*parity = 'o';
|
|
else if (frame & UARTn_FRAME_PARITY_EVEN)
|
|
*parity = 'e';
|
|
else
|
|
*parity = 'n';
|
|
|
|
*bits = (frame & UARTn_FRAME_DATABITS__MASK) -
|
|
UARTn_FRAME_DATABITS(4) + 4;
|
|
|
|
efm_debug(efm_port, "get_opts: options=%d%c%d\n",
|
|
*baud, *parity, *bits);
|
|
}
|
|
|
|
static int efm32_uart_console_setup(struct console *co, char *options)
|
|
{
|
|
struct efm32_uart_port *efm_port;
|
|
int baud = 115200;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
int ret;
|
|
|
|
if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
|
|
unsigned i;
|
|
for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
|
|
if (efm32_uart_ports[i]) {
|
|
pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
|
|
i, co->index);
|
|
co->index = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
efm_port = efm32_uart_ports[co->index];
|
|
if (!efm_port) {
|
|
pr_warn("efm32-console: No port at %d\n", co->index);
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = clk_prepare(efm_port->clk);
|
|
if (ret) {
|
|
dev_warn(efm_port->port.dev,
|
|
"console: clk_prepare failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
efm_port->port.uartclk = clk_get_rate(efm_port->clk);
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
else
|
|
efm32_uart_console_get_options(efm_port,
|
|
&baud, &parity, &bits);
|
|
|
|
return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver efm32_uart_reg;
|
|
|
|
static struct console efm32_uart_console = {
|
|
.name = DEV_NAME,
|
|
.write = efm32_uart_console_write,
|
|
.device = uart_console_device,
|
|
.setup = efm32_uart_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &efm32_uart_reg,
|
|
};
|
|
|
|
#else
|
|
#define efm32_uart_console (*(struct console *)NULL)
|
|
#endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
|
|
|
|
static struct uart_driver efm32_uart_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = DRIVER_NAME,
|
|
.dev_name = DEV_NAME,
|
|
.nr = ARRAY_SIZE(efm32_uart_ports),
|
|
.cons = &efm32_uart_console,
|
|
};
|
|
|
|
static int efm32_uart_probe_dt(struct platform_device *pdev,
|
|
struct efm32_uart_port *efm_port)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
u32 location;
|
|
int ret;
|
|
|
|
if (!np)
|
|
return 1;
|
|
|
|
ret = of_property_read_u32(np, "energymicro,location", &location);
|
|
|
|
if (ret)
|
|
/* fall back to wrongly namespaced property */
|
|
ret = of_property_read_u32(np, "efm32,location", &location);
|
|
|
|
if (ret)
|
|
/* fall back to old and (wrongly) generic property "location" */
|
|
ret = of_property_read_u32(np, "location", &location);
|
|
|
|
if (!ret) {
|
|
if (location > 5) {
|
|
dev_err(&pdev->dev, "invalid location\n");
|
|
return -EINVAL;
|
|
}
|
|
efm_debug(efm_port, "using location %u\n", location);
|
|
efm_port->pdata.location = location;
|
|
} else {
|
|
efm_debug(efm_port, "fall back to location 0\n");
|
|
}
|
|
|
|
ret = of_alias_get_id(np, "serial");
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
|
|
return ret;
|
|
} else {
|
|
efm_port->port.line = ret;
|
|
return 0;
|
|
}
|
|
|
|
}
|
|
|
|
static int efm32_uart_probe(struct platform_device *pdev)
|
|
{
|
|
struct efm32_uart_port *efm_port;
|
|
struct resource *res;
|
|
unsigned int line;
|
|
int ret;
|
|
|
|
efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
|
|
if (!efm_port) {
|
|
dev_dbg(&pdev->dev, "failed to allocate private data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
ret = -ENODEV;
|
|
dev_dbg(&pdev->dev, "failed to determine base address\n");
|
|
goto err_get_base;
|
|
}
|
|
|
|
if (resource_size(res) < 60) {
|
|
ret = -EINVAL;
|
|
dev_dbg(&pdev->dev, "memory resource too small\n");
|
|
goto err_too_small;
|
|
}
|
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret <= 0) {
|
|
dev_dbg(&pdev->dev, "failed to get rx irq\n");
|
|
goto err_get_rxirq;
|
|
}
|
|
|
|
efm_port->port.irq = ret;
|
|
|
|
ret = platform_get_irq(pdev, 1);
|
|
if (ret <= 0)
|
|
ret = efm_port->port.irq + 1;
|
|
|
|
efm_port->txirq = ret;
|
|
|
|
efm_port->port.dev = &pdev->dev;
|
|
efm_port->port.mapbase = res->start;
|
|
efm_port->port.type = PORT_EFMUART;
|
|
efm_port->port.iotype = UPIO_MEM32;
|
|
efm_port->port.fifosize = 2;
|
|
efm_port->port.ops = &efm32_uart_pops;
|
|
efm_port->port.flags = UPF_BOOT_AUTOCONF;
|
|
|
|
ret = efm32_uart_probe_dt(pdev, efm_port);
|
|
if (ret > 0) {
|
|
/* not created by device tree */
|
|
const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev);
|
|
|
|
efm_port->port.line = pdev->id;
|
|
|
|
if (pdata)
|
|
efm_port->pdata = *pdata;
|
|
} else if (ret < 0)
|
|
goto err_probe_dt;
|
|
|
|
line = efm_port->port.line;
|
|
|
|
if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
|
|
efm32_uart_ports[line] = efm_port;
|
|
|
|
ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
|
|
if (ret) {
|
|
dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
|
|
|
|
if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
|
|
efm32_uart_ports[line] = NULL;
|
|
err_probe_dt:
|
|
err_get_rxirq:
|
|
err_too_small:
|
|
err_get_base:
|
|
kfree(efm_port);
|
|
} else {
|
|
platform_set_drvdata(pdev, efm_port);
|
|
dev_dbg(&pdev->dev, "\\o/\n");
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int efm32_uart_remove(struct platform_device *pdev)
|
|
{
|
|
struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
|
|
unsigned int line = efm_port->port.line;
|
|
|
|
uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
|
|
|
|
if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
|
|
efm32_uart_ports[line] = NULL;
|
|
|
|
kfree(efm_port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id efm32_uart_dt_ids[] = {
|
|
{
|
|
.compatible = "energymicro,efm32-uart",
|
|
}, {
|
|
/* doesn't follow the "vendor,device" scheme, don't use */
|
|
.compatible = "efm32,uart",
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
|
|
|
|
static struct platform_driver efm32_uart_driver = {
|
|
.probe = efm32_uart_probe,
|
|
.remove = efm32_uart_remove,
|
|
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = efm32_uart_dt_ids,
|
|
},
|
|
};
|
|
|
|
static int __init efm32_uart_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = uart_register_driver(&efm32_uart_reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&efm32_uart_driver);
|
|
if (ret)
|
|
uart_unregister_driver(&efm32_uart_reg);
|
|
|
|
pr_info("EFM32 UART/USART driver\n");
|
|
|
|
return ret;
|
|
}
|
|
module_init(efm32_uart_init);
|
|
|
|
static void __exit efm32_uart_exit(void)
|
|
{
|
|
platform_driver_unregister(&efm32_uart_driver);
|
|
uart_unregister_driver(&efm32_uart_reg);
|
|
}
|
|
module_exit(efm32_uart_exit);
|
|
|
|
MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
|
|
MODULE_DESCRIPTION("EFM32 UART/USART driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|