![Michał Mirosław](/assets/img/avatar_default.png)
Stop the search for parent rate when exact match is found. This makes for 3 clk_round_rate() calls instead of 64 of them on SAMA5D2-based board when searching for 12.288MHz clock. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
547 lines
14 KiB
C
547 lines
14 KiB
C
/*
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* Copyright (C) 2016 Atmel Corporation,
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* Songjun Wu <songjun.wu@atmel.com>,
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* Nicolas Ferre <nicolas.ferre@atmel.com>
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* Copyright (C) 2017 Free Electrons,
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* Quentin Schulz <quentin.schulz@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
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* (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
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* its own parent. PMC and PAD can then divide the FRAC rate to best match the
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* asked rate.
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*
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* Traits of FRAC clock:
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* enable - clk_enable writes nd, fracr parameters and enables PLL
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* rate - rate is adjustable.
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* clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
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* parent - fixed parent. No clk_set_parent support
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*
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* Traits of PMC clock:
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* enable - clk_enable writes qdpmc, and enables PMC output
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* rate - rate is adjustable.
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* clk->rate = parent->rate / (qdpmc + 1)
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* parent - fixed parent. No clk_set_parent support
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*
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* Traits of PAD clock:
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* enable - clk_enable writes divisors and enables PAD output
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* rate - rate is adjustable.
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* clk->rate = parent->rate / (qdaudio * div))
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* parent - fixed parent. No clk_set_parent support
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "pmc.h"
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#define AUDIO_PLL_DIV_FRAC BIT(22)
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#define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \
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AT91_PMC_AUDIO_PLL_ND_OFFSET)
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#define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \
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AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \
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(AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
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AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK))
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#define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \
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AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
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#define AUDIO_PLL_FOUT_MIN 620000000UL
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#define AUDIO_PLL_FOUT_MAX 700000000UL
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struct clk_audio_frac {
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struct clk_hw hw;
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struct regmap *regmap;
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u32 fracr;
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u8 nd;
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};
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struct clk_audio_pad {
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struct clk_hw hw;
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struct regmap *regmap;
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u8 qdaudio;
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u8 div;
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};
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struct clk_audio_pmc {
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struct clk_hw hw;
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struct regmap *regmap;
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u8 qdpmc;
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};
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#define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw)
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#define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw)
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#define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw)
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static int clk_audio_pll_frac_enable(struct clk_hw *hw)
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{
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struct clk_audio_frac *frac = to_clk_audio_frac(hw);
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regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_RESETN, 0);
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regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_RESETN,
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AT91_PMC_AUDIO_PLL_RESETN);
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regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1,
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AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr);
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/*
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* reset and enable have to be done in 2 separated writes
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* for AT91_PMC_AUDIO_PLL0
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*/
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regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_PLLEN |
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AT91_PMC_AUDIO_PLL_ND_MASK,
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AT91_PMC_AUDIO_PLL_PLLEN |
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AT91_PMC_AUDIO_PLL_ND(frac->nd));
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return 0;
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}
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static int clk_audio_pll_pad_enable(struct clk_hw *hw)
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{
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struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
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regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1,
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AT91_PMC_AUDIO_PLL_QDPAD_MASK,
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AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div));
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regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN);
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return 0;
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}
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static int clk_audio_pll_pmc_enable(struct clk_hw *hw)
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{
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struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
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regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_PMCEN |
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AT91_PMC_AUDIO_PLL_QDPMC_MASK,
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AT91_PMC_AUDIO_PLL_PMCEN |
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AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc));
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return 0;
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}
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static void clk_audio_pll_frac_disable(struct clk_hw *hw)
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{
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struct clk_audio_frac *frac = to_clk_audio_frac(hw);
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regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_PLLEN, 0);
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/* do it in 2 separated writes */
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regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_RESETN, 0);
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}
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static void clk_audio_pll_pad_disable(struct clk_hw *hw)
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{
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struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
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regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_PADEN, 0);
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}
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static void clk_audio_pll_pmc_disable(struct clk_hw *hw)
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{
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struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
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regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
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AT91_PMC_AUDIO_PLL_PMCEN, 0);
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}
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static unsigned long clk_audio_pll_fout(unsigned long parent_rate,
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unsigned long nd, unsigned long fracr)
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{
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unsigned long long fr = (unsigned long long)parent_rate * fracr;
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pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
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fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC);
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pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
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return parent_rate * (nd + 1) + fr;
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}
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static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_audio_frac *frac = to_clk_audio_frac(hw);
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unsigned long fout;
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fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr);
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pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__,
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fout, frac->nd, (unsigned long)frac->fracr);
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return fout;
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}
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static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
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unsigned long apad_rate = 0;
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if (apad_ck->qdaudio && apad_ck->div)
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apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);
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pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n",
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__func__, apad_rate, apad_ck->div, apad_ck->qdaudio);
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return apad_rate;
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}
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static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
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unsigned long apmc_rate = 0;
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apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);
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pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__,
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apmc_rate, apmc_ck->qdpmc);
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return apmc_rate;
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}
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static int clk_audio_pll_frac_compute_frac(unsigned long rate,
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unsigned long parent_rate,
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unsigned long *nd,
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unsigned long *fracr)
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{
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unsigned long long tmp, rem;
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if (!rate)
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return -EINVAL;
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tmp = rate;
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rem = do_div(tmp, parent_rate);
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if (!tmp || tmp >= AUDIO_PLL_ND_MAX)
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return -EINVAL;
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*nd = tmp - 1;
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tmp = rem * AUDIO_PLL_DIV_FRAC;
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tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate);
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if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK)
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return -EINVAL;
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/* we can cast here as we verified the bounds just above */
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*fracr = (unsigned long)tmp;
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return 0;
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}
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static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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unsigned long fracr, nd;
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int ret;
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pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__,
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req->rate, req->best_parent_rate);
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req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX);
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req->min_rate = max(req->min_rate, AUDIO_PLL_FOUT_MIN);
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req->max_rate = min(req->max_rate, AUDIO_PLL_FOUT_MAX);
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ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate,
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&nd, &fracr);
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if (ret)
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return ret;
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req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr);
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req->best_parent_hw = clk_hw_get_parent(hw);
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pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n",
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__func__, req->rate, nd, fracr);
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return 0;
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}
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static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_hw *pclk = clk_hw_get_parent(hw);
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long best_rate = -EINVAL;
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unsigned long best_parent_rate;
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unsigned long tmp_qd;
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u32 div;
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long tmp_rate;
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int tmp_diff;
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int best_diff = -1;
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pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
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rate, *parent_rate);
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/*
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* Rate divisor is actually made of two different divisors, multiplied
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* between themselves before dividing the rate.
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* tmp_qd goes from 1 to 31 and div is either 2 or 3.
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* In order to avoid testing twice the rate divisor (e.g. divisor 12 can
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* be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop
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* for a rate divisor when div is 2 and tmp_qd is a multiple of 3.
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* We cannot inverse it (condition div is 3 and tmp_qd is even) or we
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* would miss some rate divisor that aren't reachable with div being 2
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* (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus
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* tmp_qd is even so we skip it because we think div 2 could make this
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* rate divisor which isn't possible since tmp_qd has to be <= 31).
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*/
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for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++)
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for (div = 2; div <= 3; div++) {
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if (div == 2 && tmp_qd % 3 == 0)
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continue;
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best_parent_rate = clk_hw_round_rate(pclk,
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rate * tmp_qd * div);
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tmp_rate = best_parent_rate / (div * tmp_qd);
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tmp_diff = abs(rate - tmp_rate);
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if (best_diff < 0 || best_diff > tmp_diff) {
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*parent_rate = best_parent_rate;
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best_rate = tmp_rate;
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best_diff = tmp_diff;
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}
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}
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pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
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__func__, best_rate, best_parent_rate);
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return best_rate;
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}
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static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_hw *pclk = clk_hw_get_parent(hw);
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long best_rate = -EINVAL;
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unsigned long best_parent_rate = 0;
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u32 tmp_qd = 0, div;
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long tmp_rate;
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int tmp_diff;
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int best_diff = -1;
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pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
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rate, *parent_rate);
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if (!rate)
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return 0;
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best_parent_rate = clk_round_rate(pclk->clk, 1);
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div = max(best_parent_rate / rate, 1UL);
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for (; div <= AUDIO_PLL_QDPMC_MAX; div++) {
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best_parent_rate = clk_round_rate(pclk->clk, rate * div);
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tmp_rate = best_parent_rate / div;
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tmp_diff = abs(rate - tmp_rate);
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if (best_diff < 0 || best_diff > tmp_diff) {
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*parent_rate = best_parent_rate;
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best_rate = tmp_rate;
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best_diff = tmp_diff;
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tmp_qd = div;
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if (!best_diff)
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break; /* got exact match */
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}
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}
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pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n",
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__func__, best_rate, *parent_rate, tmp_qd - 1);
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return best_rate;
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}
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static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_audio_frac *frac = to_clk_audio_frac(hw);
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unsigned long fracr, nd;
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int ret;
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pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
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parent_rate);
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if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX)
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return -EINVAL;
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ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr);
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if (ret)
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return ret;
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frac->nd = nd;
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frac->fracr = fracr;
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return 0;
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}
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static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
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u8 tmp_div;
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pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
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rate, parent_rate);
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if (!rate)
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return -EINVAL;
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tmp_div = parent_rate / rate;
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if (tmp_div % 3 == 0) {
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apad_ck->qdaudio = tmp_div / 3;
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apad_ck->div = 3;
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} else {
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apad_ck->qdaudio = tmp_div / 2;
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apad_ck->div = 2;
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}
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return 0;
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}
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static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
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if (!rate)
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return -EINVAL;
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pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
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rate, parent_rate);
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apmc_ck->qdpmc = parent_rate / rate - 1;
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return 0;
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}
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static const struct clk_ops audio_pll_frac_ops = {
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.enable = clk_audio_pll_frac_enable,
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.disable = clk_audio_pll_frac_disable,
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.recalc_rate = clk_audio_pll_frac_recalc_rate,
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.determine_rate = clk_audio_pll_frac_determine_rate,
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.set_rate = clk_audio_pll_frac_set_rate,
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};
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static const struct clk_ops audio_pll_pad_ops = {
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.enable = clk_audio_pll_pad_enable,
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.disable = clk_audio_pll_pad_disable,
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.recalc_rate = clk_audio_pll_pad_recalc_rate,
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.round_rate = clk_audio_pll_pad_round_rate,
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.set_rate = clk_audio_pll_pad_set_rate,
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};
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static const struct clk_ops audio_pll_pmc_ops = {
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.enable = clk_audio_pll_pmc_enable,
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.disable = clk_audio_pll_pmc_disable,
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.recalc_rate = clk_audio_pll_pmc_recalc_rate,
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.round_rate = clk_audio_pll_pmc_round_rate,
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.set_rate = clk_audio_pll_pmc_set_rate,
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};
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struct clk_hw * __init
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|
at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
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|
const char *parent_name)
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|
{
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|
struct clk_audio_frac *frac_ck;
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struct clk_init_data init = {};
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|
int ret;
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|
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frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
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if (!frac_ck)
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return ERR_PTR(-ENOMEM);
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|
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init.name = name;
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init.ops = &audio_pll_frac_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_SET_RATE_GATE;
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|
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frac_ck->hw.init = &init;
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frac_ck->regmap = regmap;
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|
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ret = clk_hw_register(NULL, &frac_ck->hw);
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|
if (ret) {
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|
kfree(frac_ck);
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|
return ERR_PTR(ret);
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|
}
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|
|
|
return &frac_ck->hw;
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|
}
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|
|
|
struct clk_hw * __init
|
|
at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
|
|
const char *parent_name)
|
|
{
|
|
struct clk_audio_pad *apad_ck;
|
|
struct clk_init_data init;
|
|
int ret;
|
|
|
|
apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
|
|
if (!apad_ck)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
init.name = name;
|
|
init.ops = &audio_pll_pad_ops;
|
|
init.parent_names = &parent_name;
|
|
init.num_parents = 1;
|
|
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
|
CLK_SET_RATE_PARENT;
|
|
|
|
apad_ck->hw.init = &init;
|
|
apad_ck->regmap = regmap;
|
|
|
|
ret = clk_hw_register(NULL, &apad_ck->hw);
|
|
if (ret) {
|
|
kfree(apad_ck);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
return &apad_ck->hw;
|
|
}
|
|
|
|
struct clk_hw * __init
|
|
at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
|
|
const char *parent_name)
|
|
{
|
|
struct clk_audio_pmc *apmc_ck;
|
|
struct clk_init_data init;
|
|
int ret;
|
|
|
|
apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
|
|
if (!apmc_ck)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
init.name = name;
|
|
init.ops = &audio_pll_pmc_ops;
|
|
init.parent_names = &parent_name;
|
|
init.num_parents = 1;
|
|
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
|
CLK_SET_RATE_PARENT;
|
|
|
|
apmc_ck->hw.init = &init;
|
|
apmc_ck->regmap = regmap;
|
|
|
|
ret = clk_hw_register(NULL, &apmc_ck->hw);
|
|
if (ret) {
|
|
kfree(apmc_ck);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
return &apmc_ck->hw;
|
|
}
|