60 lines
1.3 KiB
Plaintext
60 lines
1.3 KiB
Plaintext
Qualcomm adreno/snapdragon display controller
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Required properties:
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- compatible:
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* "qcom,mdp4" - mdp4
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* "qcom,mdp5" - mdp5
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt signal from the display controller.
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- connectors: array of phandles for output device(s)
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- clocks: device clocks
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See ../clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required.
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For MDP4:
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* "core_clk"
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* "iface_clk"
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* "lut_clk"
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* "src_clk"
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* "hdmi_clk"
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* "mdp_clk"
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For MDP5:
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* "bus_clk"
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* "iface_clk"
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* "core_clk_src"
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* "core_clk"
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* "lut_clk" (some MDP5 versions may not need this)
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* "vsync_clk"
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Optional properties:
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- gpus: phandle for gpu device
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- clock-names: the following clocks are optional:
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* "lut_clk"
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Example:
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/ {
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...
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mdp: qcom,mdp@5100000 {
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compatible = "qcom,mdp4";
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reg = <0x05100000 0xf0000>;
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interrupts = <GIC_SPI 75 0>;
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connectors = <&hdmi>;
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gpus = <&gpu>;
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clock-names =
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"core_clk",
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"iface_clk",
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"lut_clk",
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"src_clk",
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"hdmi_clk",
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"mdp_clk";
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clocks =
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<&mmcc MDP_SRC>,
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<&mmcc MDP_AHB_CLK>,
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<&mmcc MDP_LUT_CLK>,
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<&mmcc TV_SRC>,
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<&mmcc HDMI_TV_CLK>,
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<&mmcc MDP_TV_CLK>;
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};
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};
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