Marc Zyngier 95b861a4a6 arm64: arch_timer: Add workaround for ARM erratum 1188873 ... When running on Cortex-A76, a timer access from an AArch32 EL0 task may end up with a corrupted value or register. The workaround for this is to trap these accesses at EL1/EL2 and execute them there. This only affects versions r0p0, r1p0 and r2p0 of the CPU. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2018-10-01 13:38:47 +01:00
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asm	arm64: arch_timer: Add workaround for ARM erratum 1188873	2018-10-01 13:38:47 +01:00
uapi/asm	arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3	2018-09-14 17:46:19 +01:00