![Vladimir Murzin](/assets/img/avatar_default.png)
Common Not Private (CNP) is a feature of ARMv8.2 extension which allows translation table entries to be shared between different PEs in the same inner shareable domain, so the hardware can use this fact to optimise the caching of such entries in the TLB. CNP occupies one bit in TTBRx_ELy and VTTBR_EL2, which advertises to the hardware that the translation table entries pointed to by this TTBR are the same as every PE in the same inner shareable domain for which the equivalent TTBR also has CNP bit set. In case CNP bit is set but TTBR does not point at the same translation table entries for a given ASID and VMID, then the system is mis-configured, so the results of translations are UNPREDICTABLE. For kernel we postpone setting CNP till all cpus are up and rely on cpufeature framework to 1) patch the code which is sensitive to CNP and 2) update TTBR1_EL1 with CNP bit set. TTBR1_EL1 can be reprogrammed as result of hibernation or cpuidle (via __enable_mmu). For these two cases we restore CnP bit via __cpu_suspend_exit(). There are a few cases we need to care of changes in TTBR0_EL1: - a switch to idmap - software emulated PAN we rule out latter via Kconfig options and for the former we make sure that CNP is set for non-zero ASIDs only. Reviewed-by: James Morse <james.morse@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> [catalin.marinas@arm.com: default y for CONFIG_ARM64_CNP] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
279 lines
7.8 KiB
C
279 lines
7.8 KiB
C
/*
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* Based on arch/arm/mm/context.c
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*
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* Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bitops.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <asm/cpufeature.h>
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#include <asm/mmu_context.h>
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#include <asm/smp.h>
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#include <asm/tlbflush.h>
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static u32 asid_bits;
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static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
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static atomic64_t asid_generation;
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static unsigned long *asid_map;
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static DEFINE_PER_CPU(atomic64_t, active_asids);
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static DEFINE_PER_CPU(u64, reserved_asids);
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static cpumask_t tlb_flush_pending;
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#define ASID_MASK (~GENMASK(asid_bits - 1, 0))
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#define ASID_FIRST_VERSION (1UL << asid_bits)
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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#define NUM_USER_ASIDS (ASID_FIRST_VERSION >> 1)
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#define asid2idx(asid) (((asid) & ~ASID_MASK) >> 1)
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#define idx2asid(idx) (((idx) << 1) & ~ASID_MASK)
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#else
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#define NUM_USER_ASIDS (ASID_FIRST_VERSION)
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#define asid2idx(asid) ((asid) & ~ASID_MASK)
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#define idx2asid(idx) asid2idx(idx)
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#endif
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/* Get the ASIDBits supported by the current CPU */
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static u32 get_cpu_asid_bits(void)
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{
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u32 asid;
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int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1),
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ID_AA64MMFR0_ASID_SHIFT);
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switch (fld) {
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default:
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pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
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smp_processor_id(), fld);
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/* Fallthrough */
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case 0:
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asid = 8;
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break;
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case 2:
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asid = 16;
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}
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return asid;
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}
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/* Check if the current cpu's ASIDBits is compatible with asid_bits */
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void verify_cpu_asid_bits(void)
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{
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u32 asid = get_cpu_asid_bits();
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if (asid < asid_bits) {
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/*
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* We cannot decrease the ASID size at runtime, so panic if we support
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* fewer ASID bits than the boot CPU.
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*/
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pr_crit("CPU%d: smaller ASID size(%u) than boot CPU (%u)\n",
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smp_processor_id(), asid, asid_bits);
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cpu_panic_kernel();
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}
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}
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static void flush_context(unsigned int cpu)
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{
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int i;
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u64 asid;
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/* Update the list of reserved ASIDs and the ASID bitmap. */
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bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
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for_each_possible_cpu(i) {
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asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);
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/*
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* If this CPU has already been through a
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* rollover, but hasn't run another task in
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* the meantime, we must preserve its reserved
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* ASID, as this is the only trace we have of
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* the process it is still running.
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*/
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if (asid == 0)
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asid = per_cpu(reserved_asids, i);
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__set_bit(asid2idx(asid), asid_map);
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per_cpu(reserved_asids, i) = asid;
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}
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/*
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* Queue a TLB invalidation for each CPU to perform on next
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* context-switch
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*/
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cpumask_setall(&tlb_flush_pending);
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}
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static bool check_update_reserved_asid(u64 asid, u64 newasid)
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{
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int cpu;
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bool hit = false;
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/*
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* Iterate over the set of reserved ASIDs looking for a match.
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* If we find one, then we can update our mm to use newasid
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* (i.e. the same ASID in the current generation) but we can't
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* exit the loop early, since we need to ensure that all copies
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* of the old ASID are updated to reflect the mm. Failure to do
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* so could result in us missing the reserved ASID in a future
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* generation.
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*/
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for_each_possible_cpu(cpu) {
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if (per_cpu(reserved_asids, cpu) == asid) {
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hit = true;
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per_cpu(reserved_asids, cpu) = newasid;
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}
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}
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return hit;
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}
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static u64 new_context(struct mm_struct *mm, unsigned int cpu)
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{
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static u32 cur_idx = 1;
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u64 asid = atomic64_read(&mm->context.id);
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u64 generation = atomic64_read(&asid_generation);
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if (asid != 0) {
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u64 newasid = generation | (asid & ~ASID_MASK);
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/*
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* If our current ASID was active during a rollover, we
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* can continue to use it and this was just a false alarm.
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*/
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if (check_update_reserved_asid(asid, newasid))
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return newasid;
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/*
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* We had a valid ASID in a previous life, so try to re-use
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* it if possible.
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*/
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if (!__test_and_set_bit(asid2idx(asid), asid_map))
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return newasid;
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}
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/*
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* Allocate a free ASID. If we can't find one, take a note of the
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* currently active ASIDs and mark the TLBs as requiring flushes. We
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* always count from ASID #2 (index 1), as we use ASID #0 when setting
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* a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd
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* pairs.
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*/
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asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
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if (asid != NUM_USER_ASIDS)
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goto set_asid;
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/* We're out of ASIDs, so increment the global generation count */
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generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION,
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&asid_generation);
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flush_context(cpu);
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/* We have more ASIDs than CPUs, so this will always succeed */
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asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
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set_asid:
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__set_bit(asid, asid_map);
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cur_idx = asid;
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return idx2asid(asid) | generation;
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}
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void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
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{
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unsigned long flags;
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u64 asid, old_active_asid;
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if (system_supports_cnp())
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cpu_set_reserved_ttbr0();
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asid = atomic64_read(&mm->context.id);
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/*
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* The memory ordering here is subtle.
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* If our active_asids is non-zero and the ASID matches the current
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* generation, then we update the active_asids entry with a relaxed
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* cmpxchg. Racing with a concurrent rollover means that either:
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*
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* - We get a zero back from the cmpxchg and end up waiting on the
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* lock. Taking the lock synchronises with the rollover and so
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* we are forced to see the updated generation.
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*
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* - We get a valid ASID back from the cmpxchg, which means the
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* relaxed xchg in flush_context will treat us as reserved
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* because atomic RmWs are totally ordered for a given location.
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*/
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old_active_asid = atomic64_read(&per_cpu(active_asids, cpu));
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if (old_active_asid &&
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!((asid ^ atomic64_read(&asid_generation)) >> asid_bits) &&
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atomic64_cmpxchg_relaxed(&per_cpu(active_asids, cpu),
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old_active_asid, asid))
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goto switch_mm_fastpath;
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raw_spin_lock_irqsave(&cpu_asid_lock, flags);
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/* Check that our ASID belongs to the current generation. */
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asid = atomic64_read(&mm->context.id);
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if ((asid ^ atomic64_read(&asid_generation)) >> asid_bits) {
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asid = new_context(mm, cpu);
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atomic64_set(&mm->context.id, asid);
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}
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if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
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local_flush_tlb_all();
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atomic64_set(&per_cpu(active_asids, cpu), asid);
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raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
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switch_mm_fastpath:
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arm64_apply_bp_hardening();
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/*
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* Defer TTBR0_EL1 setting for user threads to uaccess_enable() when
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* emulating PAN.
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*/
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if (!system_uses_ttbr0_pan())
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cpu_switch_mm(mm->pgd, mm);
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}
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/* Errata workaround post TTBRx_EL1 update. */
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asmlinkage void post_ttbr_update_workaround(void)
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{
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asm(ALTERNATIVE("nop; nop; nop",
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"ic iallu; dsb nsh; isb",
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ARM64_WORKAROUND_CAVIUM_27456,
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CONFIG_CAVIUM_ERRATUM_27456));
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}
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static int asids_init(void)
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{
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asid_bits = get_cpu_asid_bits();
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/*
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* Expect allocation after rollover to fail if we don't have at least
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* one more ASID than CPUs. ASID #0 is reserved for init_mm.
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*/
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WARN_ON(NUM_USER_ASIDS - 1 <= num_possible_cpus());
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atomic64_set(&asid_generation, ASID_FIRST_VERSION);
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asid_map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS), sizeof(*asid_map),
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GFP_KERNEL);
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if (!asid_map)
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panic("Failed to allocate bitmap for %lu ASIDs\n",
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NUM_USER_ASIDS);
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pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
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return 0;
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}
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early_initcall(asids_init);
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