![Kristina Martsenko](/assets/img/avatar_default.png)
The top 4 bits of a 52-bit physical address are positioned at bits 2..5 in the TTBR registers. Introduce a couple of macros to move the bits there, and change all TTBR writers to use them. Leave TTBR0 PAN code unchanged, to avoid complicating it. A system with 52-bit PA will have PAN anyway (because it's ARMv8.1 or later), and a system without 52-bit PA can only use up to 48-bit PAs. A later patch in this series will add a kconfig dependency to ensure PAN is configured. In addition, when using 52-bit PA there is a special alignment requirement on the top-level table. We don't currently have any VA_BITS configuration that would violate the requirement, but one could be added in the future, so add a compile-time BUG_ON to check for it. Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Bob Picco <bob.picco@oracle.com> Reviewed-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> [catalin.marinas@arm.com: added TTBR_BADD_MASK_52 comment] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/*
|
|
* PGD allocation/freeing
|
|
*
|
|
* Copyright (C) 2012 ARM Ltd.
|
|
* Author: Catalin Marinas <catalin.marinas@arm.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include <linux/mm.h>
|
|
#include <linux/gfp.h>
|
|
#include <linux/highmem.h>
|
|
#include <linux/slab.h>
|
|
|
|
#include <asm/pgalloc.h>
|
|
#include <asm/page.h>
|
|
#include <asm/tlbflush.h>
|
|
|
|
static struct kmem_cache *pgd_cache __ro_after_init;
|
|
|
|
pgd_t *pgd_alloc(struct mm_struct *mm)
|
|
{
|
|
if (PGD_SIZE == PAGE_SIZE)
|
|
return (pgd_t *)__get_free_page(PGALLOC_GFP);
|
|
else
|
|
return kmem_cache_alloc(pgd_cache, PGALLOC_GFP);
|
|
}
|
|
|
|
void pgd_free(struct mm_struct *mm, pgd_t *pgd)
|
|
{
|
|
if (PGD_SIZE == PAGE_SIZE)
|
|
free_page((unsigned long)pgd);
|
|
else
|
|
kmem_cache_free(pgd_cache, pgd);
|
|
}
|
|
|
|
void __init pgd_cache_init(void)
|
|
{
|
|
if (PGD_SIZE == PAGE_SIZE)
|
|
return;
|
|
|
|
#ifdef CONFIG_ARM64_PA_BITS_52
|
|
/*
|
|
* With 52-bit physical addresses, the architecture requires the
|
|
* top-level table to be aligned to at least 64 bytes.
|
|
*/
|
|
BUILD_BUG_ON(PGD_SIZE < 64);
|
|
#endif
|
|
|
|
/*
|
|
* Naturally aligned pgds required by the architecture.
|
|
*/
|
|
pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE,
|
|
SLAB_PANIC, NULL);
|
|
}
|