529c4b05a3
The top 4 bits of a 52-bit physical address are positioned at bits 2..5 in the TTBR registers. Introduce a couple of macros to move the bits there, and change all TTBR writers to use them. Leave TTBR0 PAN code unchanged, to avoid complicating it. A system with 52-bit PA will have PAN anyway (because it's ARMv8.1 or later), and a system without 52-bit PA can only use up to 48-bit PAs. A later patch in this series will add a kconfig dependency to ensure PAN is configured. In addition, when using 52-bit PA there is a special alignment requirement on the top-level table. We don't currently have any VA_BITS configuration that would violate the requirement, but one could be added in the future, so add a compile-time BUG_ON to check for it. Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Bob Picco <bob.picco@oracle.com> Reviewed-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> [catalin.marinas@arm.com: added TTBR_BADD_MASK_52 comment] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/*
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* PGD allocation/freeing
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/mm.h>
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#include <linux/gfp.h>
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#include <linux/highmem.h>
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#include <linux/slab.h>
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#include <asm/pgalloc.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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static struct kmem_cache *pgd_cache __ro_after_init;
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pgd_t *pgd_alloc(struct mm_struct *mm)
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{
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if (PGD_SIZE == PAGE_SIZE)
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return (pgd_t *)__get_free_page(PGALLOC_GFP);
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else
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return kmem_cache_alloc(pgd_cache, PGALLOC_GFP);
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}
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void pgd_free(struct mm_struct *mm, pgd_t *pgd)
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{
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if (PGD_SIZE == PAGE_SIZE)
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free_page((unsigned long)pgd);
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else
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kmem_cache_free(pgd_cache, pgd);
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}
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void __init pgd_cache_init(void)
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{
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if (PGD_SIZE == PAGE_SIZE)
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return;
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#ifdef CONFIG_ARM64_PA_BITS_52
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/*
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* With 52-bit physical addresses, the architecture requires the
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* top-level table to be aligned to at least 64 bytes.
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*/
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BUILD_BUG_ON(PGD_SIZE < 64);
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#endif
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/*
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* Naturally aligned pgds required by the architecture.
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*/
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pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE,
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SLAB_PANIC, NULL);
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}
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