![Michael Hennerich](/assets/img/avatar_default.png)
New driver for AD7190/AD7192/AD7195 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA These devices features a dual use data out ready DOUT/RDY output. In order to avoid contentions on the SPI bus, it's necessary to use spi bus locking. The DOUT/RDY output must also be wired to an interrupt capable GPIO. In INDIO_RING_TRIGGERED mode, this driver may block its SPI bus segment for an extended period of time. Changes since V1: Add missing documentation. Remove obsoleted include files. Fix typos and style issues. Fix buffer size. Split ad7192_show() into two functions. Avoid race condition add mutex. Abandon IIO_CHAN macro. Reorder elements in ad7192_platform_data. Remove driver bus type. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Acked-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
/*
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* AD7190 AD7192 AD7195 SPI ADC driver
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*
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* Copyright 2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#ifndef IIO_ADC_AD7192_H_
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#define IIO_ADC_AD7192_H_
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/*
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* TODO: struct ad7192_platform_data needs to go into include/linux/iio
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*/
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/**
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* struct ad7192_platform_data - platform/board specific information
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* @vref_mv: the external reference voltage in millivolt
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* @clock_source_sel: [0..3]
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* 0 External 4.92 MHz clock connected from MCLK1 to MCLK2
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* 1 External Clock applied to MCLK2
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* 2 Internal 4.92 MHz Clock not available at the MCLK2 pin
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* 3 Internal 4.92 MHz Clock available at the MCLK2 pin
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* @ext_clk_Hz: the external clock frequency in Hz, if not set
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* the driver uses the internal clock (16.776 MHz)
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* @refin2_en: REFIN1/REFIN2 Reference Select (AD7190/2 only)
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* @rej60_en: 50/60Hz notch filter enable
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* @sinc3_en: SINC3 filter enable (default SINC4)
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* @chop_en: CHOP mode enable
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* @buf_en: buffered input mode enable
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* @unipolar_en: unipolar mode enable
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* @burnout_curr_en: constant current generators on AIN(+|-) enable
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*/
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struct ad7192_platform_data {
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u16 vref_mv;
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u8 clock_source_sel;
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u32 ext_clk_Hz;
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bool refin2_en;
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bool rej60_en;
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bool sinc3_en;
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bool chop_en;
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bool buf_en;
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bool unipolar_en;
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bool burnout_curr_en;
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};
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#endif /* IIO_ADC_AD7192_H_ */
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