![Lars-Peter Clausen](/assets/img/avatar_default.png)
The ad7794/ad7795 are similar to the ad7792/ad7793, but have 6 channels instead of 3. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
116 lines
4.9 KiB
C
116 lines
4.9 KiB
C
/*
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* AD7792/AD7793 SPI ADC driver
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*
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* Copyright 2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#ifndef IIO_ADC_AD7793_H_
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#define IIO_ADC_AD7793_H_
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/*
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* TODO: struct ad7793_platform_data needs to go into include/linux/iio
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*/
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/* Registers */
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#define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */
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#define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */
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#define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
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#define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */
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#define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */
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#define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */
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#define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */
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#define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit
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* (AD7792)/24-bit (AD7793)) */
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#define AD7793_REG_FULLSALE 7 /* Full-Scale Register
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* (RW, 16-bit (AD7792)/24-bit (AD7793)) */
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/* Communications Register Bit Designations (AD7793_REG_COMM) */
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#define AD7793_COMM_WEN (1 << 7) /* Write Enable */
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#define AD7793_COMM_WRITE (0 << 6) /* Write Operation */
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#define AD7793_COMM_READ (1 << 6) /* Read Operation */
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#define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
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#define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
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/* Status Register Bit Designations (AD7793_REG_STAT) */
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#define AD7793_STAT_RDY (1 << 7) /* Ready */
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#define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
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#define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */
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#define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */
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#define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */
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/* Mode Register Bit Designations (AD7793_REG_MODE) */
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#define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
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#define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
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#define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */
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#define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
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#define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */
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#define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */
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#define AD7793_MODE_IDLE 2 /* Idle Mode */
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#define AD7793_MODE_PWRDN 3 /* Power-Down Mode */
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#define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
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#define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
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#define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
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#define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
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#define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not
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* available at the CLK pin */
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#define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available
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* at the CLK pin */
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#define AD7793_CLK_EXT 2 /* External 64 kHz Clock */
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#define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */
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/* Configuration Register Bit Designations (AD7793_REG_CONF) */
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#define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage
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* Generator Enable */
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#define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */
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#define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */
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#define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */
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#define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */
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#define AD7793_CONF_REFSEL (1 << 7) /* INT/EXT Reference Select */
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#define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
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#define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */
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#define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */
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#define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */
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#define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */
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#define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */
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#define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */
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#define AD7793_CH_TEMP 6 /* Temp Sensor */
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#define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */
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#define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */
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#define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */
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#define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */
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#define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */
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/* ID Register Bit Designations (AD7793_REG_ID) */
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#define AD7792_ID 0xA
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#define AD7793_ID 0xB
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#define AD7795_ID 0xF
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#define AD7793_ID_MASK 0xF
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/* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */
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#define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1,
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* IEXC2 connect to IOUT2 */
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#define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2,
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* IEXC2 connect to IOUT1 */
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#define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources
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* IEXC1,2 connect to IOUT1 */
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#define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources
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* IEXC1,2 connect to IOUT2 */
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#define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */
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#define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */
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#define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
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struct ad7793_platform_data {
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u16 vref_mv;
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u16 mode;
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u16 conf;
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u8 io;
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};
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#endif /* IIO_ADC_AD7793_H_ */
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