![Maciej W. Rozycki](/assets/img/avatar_default.png)
Use alternatives to select the workaround for the 11AP Pentium erratum for the affected steppings on the fly rather than build time. Remove the X86_GOOD_APIC configuration option and replace all the calls to apic_write_around() with plain apic_write(), protecting accesses to the ESR as appropriate due to the 3AP Pentium erratum. Remove apic_read_around() and all its invocations altogether as not needed. Remove apic_write_atomic() and all its implementing backends. The use of ASM_OUTPUT2() is not strictly needed for input constraints, but I have used it for readability's sake. I had the feeling no one else was brave enough to do it, so I went ahead and here it is. Verified by checking the generated assembly and tested with both a 32-bit and a 64-bit configuration, also with the 11AP "feature" forced on and verified with gdb on /proc/kcore to work as expected (as an 11AP machines are quite hard to get hands on these days). Some script complained about the use of "volatile", but apic_write() needs it for the same reason and is effectively a replacement for writel(), so I have disregarded it. I am not sure what the policy wrt defconfig files is, they are generated and there is risk of a conflict resulting from an unrelated change, so I have left changes to them out. The option will get removed from them at the next run. Some testing with machines other than mine will be needed to avoid some stupid mistake, but despite its volume, the change is not really that intrusive, so I am fairly confident that because it works for me, it will everywhere. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
195 lines
4.5 KiB
C
195 lines
4.5 KiB
C
#ifndef __ASM_MACH_APIC_H
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#define __ASM_MACH_APIC_H
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#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
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#define esr_disable (1)
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static inline int apic_id_registered(void)
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{
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return (1);
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}
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static inline cpumask_t target_cpus(void)
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{
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#if defined CONFIG_ES7000_CLUSTERED_APIC
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return CPU_MASK_ALL;
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#else
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return cpumask_of_cpu(smp_processor_id());
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#endif
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}
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#define TARGET_CPUS (target_cpus())
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#if defined CONFIG_ES7000_CLUSTERED_APIC
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#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
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#define INT_DELIVERY_MODE (dest_LowestPrio)
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#define INT_DEST_MODE (1) /* logical delivery broadcast to all procs */
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#define NO_BALANCE_IRQ (1)
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#undef WAKE_SECONDARY_VIA_INIT
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#define WAKE_SECONDARY_VIA_MIP
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#else
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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#define INT_DELIVERY_MODE (dest_Fixed)
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#define INT_DEST_MODE (0) /* phys delivery to target procs */
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#define NO_BALANCE_IRQ (0)
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#undef APIC_DEST_LOGICAL
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#define APIC_DEST_LOGICAL 0x0
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#define WAKE_SECONDARY_VIA_INIT
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#endif
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static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return 0;
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}
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static inline unsigned long check_apicid_present(int bit)
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{
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return physid_isset(bit, phys_cpu_present_map);
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}
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#define apicid_cluster(apicid) (apicid & 0xF0)
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static inline unsigned long calculate_ldr(int cpu)
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{
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unsigned long id;
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id = xapic_phys_to_log_apicid(cpu);
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return (SET_APIC_LOGICAL_ID(id));
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}
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LdR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static inline void init_apic_ldr(void)
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{
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unsigned long val;
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int cpu = smp_processor_id();
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apic_write(APIC_DFR, APIC_DFR_VALUE);
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val = calculate_ldr(cpu);
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apic_write(APIC_LDR, val);
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}
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#ifndef CONFIG_X86_GENERICARCH
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extern void enable_apic_mode(void);
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#endif
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extern int apic_version [MAX_APICS];
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static inline void setup_apic_routing(void)
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{
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int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
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printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
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(apic_version[apic] == 0x14) ?
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"Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(TARGET_CPUS)[0]);
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}
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static inline int multi_timer_check(int apic, int irq)
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{
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return 0;
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}
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static inline int apicid_to_node(int logical_apicid)
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{
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return 0;
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}
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (!mps_cpu)
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return boot_cpu_physical_apicid;
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else if (mps_cpu < NR_CPUS)
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return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
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else
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return BAD_APICID;
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}
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static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
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{
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static int id = 0;
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physid_mask_t mask;
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mask = physid_mask_of_physid(id);
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++id;
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return mask;
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}
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extern u8 cpu_2_logical_apicid[];
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/* Mapping from cpu number to logical apicid */
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static inline int cpu_to_logical_apicid(int cpu)
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{
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#ifdef CONFIG_SMP
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if (cpu >= NR_CPUS)
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return BAD_APICID;
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return (int)cpu_2_logical_apicid[cpu];
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#else
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return logical_smp_processor_id();
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#endif
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}
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static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
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{
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/* For clustered we don't have a good way to do this yet - hack */
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return physids_promote(0xff);
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}
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static inline void setup_portio_remap(void)
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{
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}
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extern unsigned int boot_cpu_physical_apicid;
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static inline int check_phys_apicid_present(int cpu_physical_apicid)
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{
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boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
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return (1);
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}
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static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int num_bits_set;
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int cpus_found = 0;
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int cpu;
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int apicid;
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num_bits_set = cpus_weight(cpumask);
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/* Return id to all */
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if (num_bits_set == NR_CPUS)
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#if defined CONFIG_ES7000_CLUSTERED_APIC
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return 0xFF;
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#else
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return cpu_to_logical_apicid(0);
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#endif
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/*
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* The cpus in the mask must all be on the apic cluster. If are not
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* on the same apicid cluster return default value of TARGET_CPUS.
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*/
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cpu = first_cpu(cpumask);
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apicid = cpu_to_logical_apicid(cpu);
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while (cpus_found < num_bits_set) {
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if (cpu_isset(cpu, cpumask)) {
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int new_apicid = cpu_to_logical_apicid(cpu);
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if (apicid_cluster(apicid) !=
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apicid_cluster(new_apicid)){
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printk ("%s: Not a valid mask!\n",__FUNCTION__);
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#if defined CONFIG_ES7000_CLUSTERED_APIC
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return 0xFF;
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#else
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return cpu_to_logical_apicid(0);
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#endif
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}
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apicid = new_apicid;
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cpus_found++;
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}
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cpu++;
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}
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return apicid;
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}
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static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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#endif /* __ASM_MACH_APIC_H */
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