![J Keerthy](/assets/img/avatar_default.png)
The patch removes all the CK_* which were used to identify the family of processors for which the individual clocks belonged to. Instead now separate lists are created based on the family of processors. Boot Tested on: OMAP4430, OMAP4460, Beagle-board, AM33X boards, OMAP2 boards. Signed-off-by: J Keerthy <j-keerthy@ti.com> Tested-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Tested-by: Jon Hunter <jon-hunter@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: changed omap_clock_register_links() to omap_clocks_register(); updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
665 lines
19 KiB
C
665 lines
19 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.c
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/clk-private.h>
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#include <asm/cpu.h>
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#include <trace/events/power.h>
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#include "soc.h"
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#include "clockdomain.h"
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#include "clock.h"
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#include "cm.h"
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#include "cm2xxx.h"
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#include "cm3xxx.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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#include "common.h"
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/*
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* MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
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* for a module to indicate that it is no longer in idle
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*/
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#define MAX_MODULE_ENABLE_WAIT 100000
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u16 cpu_mask;
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/*
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* clkdm_control: if true, then when a clock is enabled in the
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* hardware, its clockdomain will first be enabled; and when a clock
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* is disabled in the hardware, its clockdomain will be disabled
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* afterwards.
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*/
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static bool clkdm_control = true;
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static LIST_HEAD(clk_hw_omap_clocks);
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/*
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* Used for clocks that have the same value as the parent clock,
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* divided by some factor
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*/
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unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_hw_omap *oclk;
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if (!hw) {
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pr_warn("%s: hw is NULL\n", __func__);
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return -EINVAL;
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}
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oclk = to_clk_hw_omap(hw);
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WARN_ON(!oclk->fixed_div);
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return parent_rate / oclk->fixed_div;
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}
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/*
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* OMAP2+ specific clock functions
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*/
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/* Private functions */
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/**
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* _wait_idlest_generic - wait for a module to leave the idle state
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* @reg: virtual address of module IDLEST register
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* @mask: value to mask against to determine if the module is active
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* @idlest: idle state indicator (0 or 1) for the clock
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* @name: name of the clock (for printk)
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*
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* Wait for a module to leave idle, where its idle-status register is
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* not inside the CM module. Returns 1 if the module left idle
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* promptly, or 0 if the module did not leave idle before the timeout
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* elapsed. XXX Deprecated - should be moved into drivers for the
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* individual IP block that the IDLEST register exists in.
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*/
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static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
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const char *name)
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{
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int i = 0, ena = 0;
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ena = (idlest) ? 0 : mask;
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omap_test_timeout(((__raw_readl(reg) & mask) == ena),
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MAX_MODULE_ENABLE_WAIT, i);
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if (i < MAX_MODULE_ENABLE_WAIT)
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pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
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name, i);
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else
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pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
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name, MAX_MODULE_ENABLE_WAIT);
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return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
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};
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/**
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* _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
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* @clk: struct clk * belonging to the module
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*
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* If the necessary clocks for the OMAP hardware IP block that
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* corresponds to clock @clk are enabled, then wait for the module to
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* indicate readiness (i.e., to leave IDLE). This code does not
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* belong in the clock code and will be moved in the medium term to
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* module-dependent code. No return value.
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*/
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static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
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{
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void __iomem *companion_reg, *idlest_reg;
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u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
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s16 prcm_mod;
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int r;
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/* Not all modules have multiple clocks that their IDLEST depends on */
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if (clk->ops->find_companion) {
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clk->ops->find_companion(clk, &companion_reg, &other_bit);
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if (!(__raw_readl(companion_reg) & (1 << other_bit)))
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return;
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}
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clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
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r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
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if (r) {
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/* IDLEST register not in the CM module */
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_wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
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__clk_get_name(clk->hw.clk));
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} else {
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cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
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};
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}
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/* Public functions */
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/**
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* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
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* @clk: OMAP clock struct ptr to use
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*
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* Convert a clockdomain name stored in a struct clk 'clk' into a
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* clockdomain pointer, and save it into the struct clk. Intended to be
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* called during clk_register(). No return value.
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*/
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void omap2_init_clk_clkdm(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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struct clockdomain *clkdm;
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const char *clk_name;
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if (!clk->clkdm_name)
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return;
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clk_name = __clk_get_name(hw->clk);
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clkdm = clkdm_lookup(clk->clkdm_name);
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if (clkdm) {
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pr_debug("clock: associated clk %s to clkdm %s\n",
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clk_name, clk->clkdm_name);
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clk->clkdm = clkdm;
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} else {
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pr_debug("clock: could not associate clk %s to clkdm %s\n",
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clk_name, clk->clkdm_name);
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}
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}
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/**
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* omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
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*
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* Prevent the OMAP clock code from calling into the clockdomain code
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* when a hardware clock in that clockdomain is enabled or disabled.
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* Intended to be called at init time from omap*_clk_init(). No
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* return value.
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*/
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void __init omap2_clk_disable_clkdm_control(void)
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{
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clkdm_control = false;
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}
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/**
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* omap2_clk_dflt_find_companion - find companion clock to @clk
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* @clk: struct clk * to find the companion clock of
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* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
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* @other_bit: u8 ** to return the companion clock bit shift in
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*
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* Note: We don't need special code here for INVERT_ENABLE for the
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* time being since INVERT_ENABLE only applies to clocks enabled by
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* CM_CLKEN_PLL
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*
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* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
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* just a matter of XORing the bits.
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*
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* Some clocks don't have companion clocks. For example, modules with
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* only an interface clock (such as MAILBOXES) don't have a companion
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* clock. Right now, this code relies on the hardware exporting a bit
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* in the correct companion register that indicates that the
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* nonexistent 'companion clock' is active. Future patches will
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* associate this type of code with per-module data structures to
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* avoid this issue, and remove the casts. No return value.
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*/
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void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
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void __iomem **other_reg, u8 *other_bit)
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{
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u32 r;
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/*
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* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
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* it's just a matter of XORing the bits.
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*/
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r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
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*other_reg = (__force void __iomem *)r;
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*other_bit = clk->enable_bit;
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}
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/**
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* omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
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* @clk: struct clk * to find IDLEST info for
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* @idlest_reg: void __iomem ** to return the CM_IDLEST va in
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* @idlest_bit: u8 * to return the CM_IDLEST bit shift in
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* @idlest_val: u8 * to return the idle status indicator
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*
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* Return the CM_IDLEST register address and bit shift corresponding
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* to the module that "owns" this clock. This default code assumes
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* that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
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* the IDLEST register address ID corresponds to the CM_*CLKEN
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* register address ID (e.g., that CM_FCLKEN2 corresponds to
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* CM_IDLEST2). This is not true for all modules. No return value.
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*/
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void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
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void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
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{
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u32 r;
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r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
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*idlest_reg = (__force void __iomem *)r;
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*idlest_bit = clk->enable_bit;
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/*
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* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
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* 34xx reverses this, just to keep us on our toes
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* AM35xx uses both, depending on the module.
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*/
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if (cpu_is_omap24xx())
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*idlest_val = OMAP24XX_CM_IDLEST_VAL;
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else if (cpu_is_omap34xx())
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*idlest_val = OMAP34XX_CM_IDLEST_VAL;
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else
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BUG();
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}
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/**
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* omap2_dflt_clk_enable - enable a clock in the hardware
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* @hw: struct clk_hw * of the clock to enable
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*
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* Enable the clock @hw in the hardware. We first call into the OMAP
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* clockdomain code to "enable" the corresponding clockdomain if this
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* is the first enabled user of the clockdomain. Then program the
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* hardware to enable the clock. Then wait for the IP block that uses
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* this clock to leave idle (if applicable). Returns the error value
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* from clkdm_clk_enable() if it terminated with an error, or -EINVAL
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* if @hw has a null clock enable_reg, or zero upon success.
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*/
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int omap2_dflt_clk_enable(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk;
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u32 v;
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int ret = 0;
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clk = to_clk_hw_omap(hw);
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if (clkdm_control && clk->clkdm) {
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ret = clkdm_clk_enable(clk->clkdm, hw->clk);
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if (ret) {
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WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
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__func__, __clk_get_name(hw->clk),
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clk->clkdm->name, ret);
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return ret;
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}
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}
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if (unlikely(clk->enable_reg == NULL)) {
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pr_err("%s: %s missing enable_reg\n", __func__,
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__clk_get_name(hw->clk));
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ret = -EINVAL;
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goto err;
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}
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/* FIXME should not have INVERT_ENABLE bit here */
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v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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v &= ~(1 << clk->enable_bit);
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else
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v |= (1 << clk->enable_bit);
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__raw_writel(v, clk->enable_reg);
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v = __raw_readl(clk->enable_reg); /* OCP barrier */
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if (clk->ops && clk->ops->find_idlest)
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_omap2_module_wait_ready(clk);
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return 0;
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err:
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if (clkdm_control && clk->clkdm)
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clkdm_clk_disable(clk->clkdm, hw->clk);
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return ret;
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}
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/**
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* omap2_dflt_clk_disable - disable a clock in the hardware
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* @hw: struct clk_hw * of the clock to disable
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*
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* Disable the clock @hw in the hardware, and call into the OMAP
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* clockdomain code to "disable" the corresponding clockdomain if all
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* clocks/hwmods in that clockdomain are now disabled. No return
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* value.
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*/
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void omap2_dflt_clk_disable(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk;
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u32 v;
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clk = to_clk_hw_omap(hw);
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if (!clk->enable_reg) {
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/*
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* 'independent' here refers to a clock which is not
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* controlled by its parent.
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*/
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pr_err("%s: independent clock %s has no enable_reg\n",
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__func__, __clk_get_name(hw->clk));
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return;
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}
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v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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v |= (1 << clk->enable_bit);
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else
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v &= ~(1 << clk->enable_bit);
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__raw_writel(v, clk->enable_reg);
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/* No OCP barrier needed here since it is a disable operation */
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if (clkdm_control && clk->clkdm)
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clkdm_clk_disable(clk->clkdm, hw->clk);
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}
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/**
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* omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
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* @hw: struct clk_hw * of the clock being enabled
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*
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* Increment the usecount of the clockdomain of the clock pointed to
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* by @hw; if the usecount is 1, the clockdomain will be "enabled."
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* Only needed for clocks that don't use omap2_dflt_clk_enable() as
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* their enable function pointer. Passes along the return value of
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* clkdm_clk_enable(), -EINVAL if @hw is not associated with a
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* clockdomain, or 0 if clock framework-based clockdomain control is
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* not implemented.
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*/
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int omap2_clkops_enable_clkdm(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk;
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int ret = 0;
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clk = to_clk_hw_omap(hw);
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if (unlikely(!clk->clkdm)) {
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pr_err("%s: %s: no clkdm set ?!\n", __func__,
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__clk_get_name(hw->clk));
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return -EINVAL;
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}
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if (unlikely(clk->enable_reg))
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pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
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__clk_get_name(hw->clk));
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if (!clkdm_control) {
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pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
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__func__, __clk_get_name(hw->clk));
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return 0;
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}
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ret = clkdm_clk_enable(clk->clkdm, hw->clk);
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WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
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__func__, __clk_get_name(hw->clk), clk->clkdm->name, ret);
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return ret;
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}
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/**
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* omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
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* @hw: struct clk_hw * of the clock being disabled
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*
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* Decrement the usecount of the clockdomain of the clock pointed to
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* by @hw; if the usecount is 0, the clockdomain will be "disabled."
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* Only needed for clocks that don't use omap2_dflt_clk_disable() as their
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* disable function pointer. No return value.
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*/
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void omap2_clkops_disable_clkdm(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk;
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clk = to_clk_hw_omap(hw);
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if (unlikely(!clk->clkdm)) {
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pr_err("%s: %s: no clkdm set ?!\n", __func__,
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__clk_get_name(hw->clk));
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return;
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}
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if (unlikely(clk->enable_reg))
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pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
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__clk_get_name(hw->clk));
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if (!clkdm_control) {
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pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
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__func__, __clk_get_name(hw->clk));
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return;
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}
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clkdm_clk_disable(clk->clkdm, hw->clk);
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}
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/**
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* omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
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* @hw: struct clk_hw * to check
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*
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* Return 1 if the clock represented by @hw is enabled in the
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* hardware, or 0 otherwise. Intended for use in the struct
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* clk_ops.is_enabled function pointer.
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*/
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int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 v;
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v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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v ^= BIT(clk->enable_bit);
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v &= BIT(clk->enable_bit);
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return v ? 1 : 0;
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}
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static int __initdata mpurate;
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/*
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* By default we use the rate set by the bootloader.
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* You can override this with mpurate= cmdline option.
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*/
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static int __init omap_clk_setup(char *str)
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{
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get_option(&str, &mpurate);
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if (!mpurate)
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return 1;
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if (mpurate < 1000)
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mpurate *= 1000000;
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|
|
return 1;
|
|
}
|
|
__setup("mpurate=", omap_clk_setup);
|
|
|
|
/**
|
|
* omap2_init_clk_hw_omap_clocks - initialize an OMAP clock
|
|
* @clk: struct clk * to initialize
|
|
*
|
|
* Add an OMAP clock @clk to the internal list of OMAP clocks. Used
|
|
* temporarily for autoidle handling, until this support can be
|
|
* integrated into the common clock framework code in some way. No
|
|
* return value.
|
|
*/
|
|
void omap2_init_clk_hw_omap_clocks(struct clk *clk)
|
|
{
|
|
struct clk_hw_omap *c;
|
|
|
|
if (__clk_get_flags(clk) & CLK_IS_BASIC)
|
|
return;
|
|
|
|
c = to_clk_hw_omap(__clk_get_hw(clk));
|
|
list_add(&c->node, &clk_hw_omap_clocks);
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that
|
|
* support it
|
|
*
|
|
* Enable clock autoidle on all OMAP clocks that have allow_idle
|
|
* function pointers associated with them. This function is intended
|
|
* to be temporary until support for this is added to the common clock
|
|
* code. Returns 0.
|
|
*/
|
|
int omap2_clk_enable_autoidle_all(void)
|
|
{
|
|
struct clk_hw_omap *c;
|
|
|
|
list_for_each_entry(c, &clk_hw_omap_clocks, node)
|
|
if (c->ops && c->ops->allow_idle)
|
|
c->ops->allow_idle(c);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that
|
|
* support it
|
|
*
|
|
* Disable clock autoidle on all OMAP clocks that have allow_idle
|
|
* function pointers associated with them. This function is intended
|
|
* to be temporary until support for this is added to the common clock
|
|
* code. Returns 0.
|
|
*/
|
|
int omap2_clk_disable_autoidle_all(void)
|
|
{
|
|
struct clk_hw_omap *c;
|
|
|
|
list_for_each_entry(c, &clk_hw_omap_clocks, node)
|
|
if (c->ops && c->ops->deny_idle)
|
|
c->ops->deny_idle(c);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_enable_init_clocks - prepare & enable a list of clocks
|
|
* @clk_names: ptr to an array of strings of clock names to enable
|
|
* @num_clocks: number of clock names in @clk_names
|
|
*
|
|
* Prepare and enable a list of clocks, named by @clk_names. No
|
|
* return value. XXX Deprecated; only needed until these clocks are
|
|
* properly claimed and enabled by the drivers or core code that uses
|
|
* them. XXX What code disables & calls clk_put on these clocks?
|
|
*/
|
|
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
|
|
{
|
|
struct clk *init_clk;
|
|
int i;
|
|
|
|
for (i = 0; i < num_clocks; i++) {
|
|
init_clk = clk_get(NULL, clk_names[i]);
|
|
clk_prepare_enable(init_clk);
|
|
}
|
|
}
|
|
|
|
const struct clk_hw_omap_ops clkhwops_wait = {
|
|
.find_idlest = omap2_clk_dflt_find_idlest,
|
|
.find_companion = omap2_clk_dflt_find_companion,
|
|
};
|
|
|
|
/**
|
|
* omap_clocks_register - register an array of omap_clk
|
|
* @ocs: pointer to an array of omap_clk to register
|
|
*/
|
|
void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
|
|
{
|
|
struct omap_clk *c;
|
|
|
|
for (c = oclks; c < oclks + cnt; c++) {
|
|
clkdev_add(&c->lk);
|
|
if (!__clk_init(NULL, c->lk.clk))
|
|
omap2_init_clk_hw_omap_clocks(c->lk.clk);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
|
|
* @mpurate_ck_name: clk name of the clock to change rate
|
|
*
|
|
* Change the ARM MPU clock rate to the rate specified on the command
|
|
* line, if one was specified. @mpurate_ck_name should be
|
|
* "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
|
|
* XXX Does not handle voltage scaling - on OMAP2xxx this is currently
|
|
* handled by the virt_prcm_set clock, but this should be handled by
|
|
* the OPP layer. XXX This is intended to be handled by the OPP layer
|
|
* code in the near future and should be removed from the clock code.
|
|
* Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
|
|
* the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
|
|
* cannot be found, or 0 upon success.
|
|
*/
|
|
int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
|
|
{
|
|
struct clk *mpurate_ck;
|
|
int r;
|
|
|
|
if (!mpurate)
|
|
return -EINVAL;
|
|
|
|
mpurate_ck = clk_get(NULL, mpurate_ck_name);
|
|
if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
|
|
return -ENOENT;
|
|
|
|
r = clk_set_rate(mpurate_ck, mpurate);
|
|
if (IS_ERR_VALUE(r)) {
|
|
WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
|
|
mpurate_ck_name, mpurate, r);
|
|
clk_put(mpurate_ck);
|
|
return -EINVAL;
|
|
}
|
|
|
|
calibrate_delay();
|
|
clk_put(mpurate_ck);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_print_new_rates - print summary of current clock tree rates
|
|
* @hfclkin_ck_name: clk name for the off-chip HF oscillator
|
|
* @core_ck_name: clk name for the on-chip CORE_CLK
|
|
* @mpu_ck_name: clk name for the ARM MPU clock
|
|
*
|
|
* Prints a short message to the console with the HFCLKIN oscillator
|
|
* rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
|
|
* Called by the boot-time MPU rate switching code. XXX This is intended
|
|
* to be handled by the OPP layer code in the near future and should be
|
|
* removed from the clock code. No return value.
|
|
*/
|
|
void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
|
|
const char *core_ck_name,
|
|
const char *mpu_ck_name)
|
|
{
|
|
struct clk *hfclkin_ck, *core_ck, *mpu_ck;
|
|
unsigned long hfclkin_rate;
|
|
|
|
mpu_ck = clk_get(NULL, mpu_ck_name);
|
|
if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
|
|
return;
|
|
|
|
core_ck = clk_get(NULL, core_ck_name);
|
|
if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
|
|
return;
|
|
|
|
hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
|
|
if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
|
|
return;
|
|
|
|
hfclkin_rate = clk_get_rate(hfclkin_ck);
|
|
|
|
pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
|
|
(hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
|
|
(clk_get_rate(core_ck) / 1000000),
|
|
(clk_get_rate(mpu_ck) / 1000000));
|
|
}
|