269 lines
7.3 KiB
C
269 lines
7.3 KiB
C
/*
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Shannon Zhao <shannon.zhao@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cpu.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include <asm/kvm_emulate.h>
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#include <kvm/arm_pmu.h>
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/**
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* kvm_pmu_get_counter_value - get PMU counter value
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* @vcpu: The vcpu pointer
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* @select_idx: The counter index
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*/
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
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{
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u64 counter, reg, enabled, running;
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc = &pmu->pmc[select_idx];
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reg = (select_idx == ARMV8_PMU_CYCLE_IDX)
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? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
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counter = vcpu_sys_reg(vcpu, reg);
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/* The real counter value is equal to the value of counter register plus
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* the value perf event counts.
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*/
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if (pmc->perf_event)
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counter += perf_event_read_value(pmc->perf_event, &enabled,
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&running);
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return counter & pmc->bitmask;
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}
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/**
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* kvm_pmu_set_counter_value - set PMU counter value
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* @vcpu: The vcpu pointer
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* @select_idx: The counter index
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* @val: The counter value
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*/
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void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
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{
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u64 reg;
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reg = (select_idx == ARMV8_PMU_CYCLE_IDX)
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? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
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vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx);
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}
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/**
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* kvm_pmu_stop_counter - stop PMU counter
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* @pmc: The PMU counter pointer
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*
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* If this counter has been configured to monitor some event, release it here.
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*/
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static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc)
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{
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u64 counter, reg;
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if (pmc->perf_event) {
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counter = kvm_pmu_get_counter_value(vcpu, pmc->idx);
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reg = (pmc->idx == ARMV8_PMU_CYCLE_IDX)
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? PMCCNTR_EL0 : PMEVCNTR0_EL0 + pmc->idx;
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vcpu_sys_reg(vcpu, reg) = counter;
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perf_event_disable(pmc->perf_event);
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perf_event_release_kernel(pmc->perf_event);
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pmc->perf_event = NULL;
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}
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}
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u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
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{
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u64 val = vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMU_PMCR_N_SHIFT;
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val &= ARMV8_PMU_PMCR_N_MASK;
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if (val == 0)
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return BIT(ARMV8_PMU_CYCLE_IDX);
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else
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return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX);
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}
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/**
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* kvm_pmu_enable_counter - enable selected PMU counter
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* @vcpu: The vcpu pointer
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* @val: the value guest writes to PMCNTENSET register
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*
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* Call perf_event_enable to start counting the perf event
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*/
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void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val)
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{
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int i;
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc;
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if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val)
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return;
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for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
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if (!(val & BIT(i)))
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continue;
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pmc = &pmu->pmc[i];
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if (pmc->perf_event) {
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perf_event_enable(pmc->perf_event);
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if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE)
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kvm_debug("fail to enable perf event\n");
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}
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}
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}
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/**
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* kvm_pmu_disable_counter - disable selected PMU counter
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* @vcpu: The vcpu pointer
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* @val: the value guest writes to PMCNTENCLR register
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*
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* Call perf_event_disable to stop counting the perf event
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*/
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void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val)
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{
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int i;
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc;
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if (!val)
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return;
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for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
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if (!(val & BIT(i)))
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continue;
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pmc = &pmu->pmc[i];
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if (pmc->perf_event)
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perf_event_disable(pmc->perf_event);
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}
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}
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static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu)
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{
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u64 reg = 0;
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if ((vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))
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reg = vcpu_sys_reg(vcpu, PMOVSSET_EL0);
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reg &= vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
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reg &= vcpu_sys_reg(vcpu, PMINTENSET_EL1);
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reg &= kvm_pmu_valid_counter_mask(vcpu);
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return reg;
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}
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/**
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* kvm_pmu_overflow_set - set PMU overflow interrupt
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* @vcpu: The vcpu pointer
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* @val: the value guest writes to PMOVSSET register
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*/
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void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val)
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{
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u64 reg;
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if (val == 0)
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return;
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vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= val;
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reg = kvm_pmu_overflow_status(vcpu);
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if (reg != 0)
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kvm_vcpu_kick(vcpu);
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}
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/**
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* kvm_pmu_software_increment - do software increment
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* @vcpu: The vcpu pointer
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* @val: the value guest writes to PMSWINC register
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*/
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void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
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{
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int i;
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u64 type, enable, reg;
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if (val == 0)
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return;
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enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
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for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) {
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if (!(val & BIT(i)))
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continue;
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type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i)
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& ARMV8_PMU_EVTYPE_EVENT;
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if ((type == ARMV8_PMU_EVTYPE_EVENT_SW_INCR)
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&& (enable & BIT(i))) {
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reg = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
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reg = lower_32_bits(reg);
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vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;
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if (!reg)
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kvm_pmu_overflow_set(vcpu, BIT(i));
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}
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}
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}
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static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx)
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{
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return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) &&
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(vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(select_idx));
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}
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/**
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* kvm_pmu_set_counter_event_type - set selected counter to monitor some event
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* @vcpu: The vcpu pointer
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* @data: The data guest writes to PMXEVTYPER_EL0
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* @select_idx: The number of selected counter
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*
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* When OS accesses PMXEVTYPER_EL0, that means it wants to set a PMC to count an
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* event with given hardware event number. Here we call perf_event API to
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* emulate this action and create a kernel perf event for it.
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*/
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void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
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u64 select_idx)
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{
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc = &pmu->pmc[select_idx];
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struct perf_event *event;
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struct perf_event_attr attr;
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u64 eventsel, counter;
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kvm_pmu_stop_counter(vcpu, pmc);
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eventsel = data & ARMV8_PMU_EVTYPE_EVENT;
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/* Software increment event does't need to be backed by a perf event */
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if (eventsel == ARMV8_PMU_EVTYPE_EVENT_SW_INCR)
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return;
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memset(&attr, 0, sizeof(struct perf_event_attr));
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attr.type = PERF_TYPE_RAW;
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attr.size = sizeof(attr);
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attr.pinned = 1;
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attr.disabled = !kvm_pmu_counter_is_enabled(vcpu, select_idx);
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attr.exclude_user = data & ARMV8_PMU_EXCLUDE_EL0 ? 1 : 0;
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attr.exclude_kernel = data & ARMV8_PMU_EXCLUDE_EL1 ? 1 : 0;
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attr.exclude_hv = 1; /* Don't count EL2 events */
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attr.exclude_host = 1; /* Don't count host events */
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attr.config = eventsel;
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counter = kvm_pmu_get_counter_value(vcpu, select_idx);
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/* The initial sample period (overflow count) of an event. */
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attr.sample_period = (-counter) & pmc->bitmask;
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event = perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc);
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if (IS_ERR(event)) {
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pr_err_once("kvm: pmu event creation failed %ld\n",
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PTR_ERR(event));
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return;
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}
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pmc->perf_event = event;
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}
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