![Benjamin Herrenschmidt](/assets/img/avatar_default.png)
This patch completely refactors DMA operations for 64 bits powerpc. 32 bits is untouched for now. We use the new dev_archdata structure to add the dma operations pointer and associated data to struct device. While at it, we also add the OF node pointer and numa node. In the future, we might want to look into merging that with pci_dn as well. The old vio, pci-iommu and pci-direct DMA ops are gone. They are now replaced by a set of generic iommu and direct DMA ops (non PCI specific) that can be used by bus types. The toplevel implementation is now inline. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
593 lines
16 KiB
C
593 lines
16 KiB
C
/*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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*
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* Rewrite, cleanup:
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*
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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* Copyright (C) 2006 Olof Johansson <olof@lixom.net>
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*
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* Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/rtas.h>
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#include <asm/iommu.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/abs_addr.h>
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#include <asm/pSeries_reconfig.h>
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#include <asm/firmware.h>
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#include <asm/tce.h>
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#include <asm/ppc-pci.h>
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#include <asm/udbg.h>
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#include "plpar_wrappers.h"
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#define DBG(fmt...)
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static void tce_build_pSeries(struct iommu_table *tbl, long index,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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u64 proto_tce;
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u64 *tcep;
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u64 rpn;
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proto_tce = TCE_PCI_READ; // Read allowed
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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tcep = ((u64 *)tbl->it_base) + index;
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while (npages--) {
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/* can't move this out since we might cross LMB boundary */
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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*tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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uaddr += TCE_PAGE_SIZE;
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tcep++;
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}
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}
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static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
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{
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u64 *tcep;
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tcep = ((u64 *)tbl->it_base) + index;
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while (npages--)
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*(tcep++) = 0;
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}
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static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
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{
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u64 *tcep;
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tcep = ((u64 *)tbl->it_base) + index;
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return *tcep;
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}
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static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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u64 rc;
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u64 proto_tce, tce;
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u64 rpn;
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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proto_tce = TCE_PCI_READ;
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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while (npages--) {
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tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
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if (rc && printk_ratelimit()) {
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printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%lx\n", (u64)tcenum);
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printk("\ttce val = 0x%lx\n", tce );
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show_stack(current, (unsigned long *)__get_SP());
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}
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tcenum++;
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rpn++;
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}
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}
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static DEFINE_PER_CPU(u64 *, tce_page) = NULL;
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static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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u64 rc;
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u64 proto_tce;
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u64 *tcep;
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u64 rpn;
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long l, limit;
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if (npages == 1)
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return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
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direction);
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tcep = __get_cpu_var(tce_page);
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/* This is safe to do since interrupts are off when we're called
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* from iommu_alloc{,_sg}()
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*/
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if (!tcep) {
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tcep = (u64 *)__get_free_page(GFP_ATOMIC);
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/* If allocation fails, fall back to the loop implementation */
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if (!tcep)
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return tce_build_pSeriesLP(tbl, tcenum, npages,
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uaddr, direction);
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__get_cpu_var(tce_page) = tcep;
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}
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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proto_tce = TCE_PCI_READ;
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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/* We can map max one pageful of TCEs at a time */
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do {
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/*
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* Set up the page with TCE data, looping through and setting
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* the values.
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*/
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limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
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for (l = 0; l < limit; l++) {
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tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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rpn++;
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}
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rc = plpar_tce_put_indirect((u64)tbl->it_index,
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(u64)tcenum << 12,
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(u64)virt_to_abs(tcep),
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limit);
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npages -= limit;
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tcenum += limit;
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} while (npages > 0 && !rc);
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if (rc && printk_ratelimit()) {
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printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\tnpages = 0x%lx\n", (u64)npages);
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printk("\ttce[0] val = 0x%lx\n", tcep[0]);
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show_stack(current, (unsigned long *)__get_SP());
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}
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}
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static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
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{
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u64 rc;
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while (npages--) {
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rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
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if (rc && printk_ratelimit()) {
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printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%lx\n", (u64)tcenum);
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show_stack(current, (unsigned long *)__get_SP());
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}
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tcenum++;
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}
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}
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static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
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{
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u64 rc;
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rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
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if (rc && printk_ratelimit()) {
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printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
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printk("\trc = %ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\tnpages = 0x%lx\n", (u64)npages);
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show_stack(current, (unsigned long *)__get_SP());
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}
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}
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static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
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{
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u64 rc;
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unsigned long tce_ret;
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rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
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if (rc && printk_ratelimit()) {
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printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n",
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rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%lx\n", (u64)tcenum);
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show_stack(current, (unsigned long *)__get_SP());
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}
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return tce_ret;
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}
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static void iommu_table_setparms(struct pci_controller *phb,
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struct device_node *dn,
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struct iommu_table *tbl)
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{
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struct device_node *node;
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const unsigned long *basep;
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const u32 *sizep;
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node = (struct device_node *)phb->arch_data;
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basep = get_property(node, "linux,tce-base", NULL);
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sizep = get_property(node, "linux,tce-size", NULL);
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if (basep == NULL || sizep == NULL) {
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printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
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"missing tce entries !\n", dn->full_name);
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return;
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}
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tbl->it_base = (unsigned long)__va(*basep);
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#ifndef CONFIG_CRASH_DUMP
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memset((void *)tbl->it_base, 0, *sizep);
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#endif
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tbl->it_busno = phb->bus->number;
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/* Units of tce entries */
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tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
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/* Test if we are going over 2GB of DMA space */
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if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
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udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
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panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
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}
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phb->dma_window_base_cur += phb->dma_window_size;
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/* Set the tce table size - measured in entries */
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tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
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tbl->it_index = 0;
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tbl->it_blocksize = 16;
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tbl->it_type = TCE_PCI;
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}
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/*
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* iommu_table_setparms_lpar
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*
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* Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
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*/
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static void iommu_table_setparms_lpar(struct pci_controller *phb,
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struct device_node *dn,
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struct iommu_table *tbl,
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const void *dma_window)
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{
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unsigned long offset, size;
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tbl->it_busno = PCI_DN(dn)->bussubno;
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of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
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tbl->it_base = 0;
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tbl->it_blocksize = 16;
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tbl->it_type = TCE_PCI;
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tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
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tbl->it_size = size >> IOMMU_PAGE_SHIFT;
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}
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static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
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{
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struct device_node *dn;
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struct iommu_table *tbl;
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struct device_node *isa_dn, *isa_dn_orig;
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struct device_node *tmp;
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struct pci_dn *pci;
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int children;
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dn = pci_bus_to_OF_node(bus);
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DBG("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
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if (bus->self) {
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/* This is not a root bus, any setup will be done for the
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* device-side of the bridge in iommu_dev_setup_pSeries().
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*/
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return;
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}
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pci = PCI_DN(dn);
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/* Check if the ISA bus on the system is under
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* this PHB.
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*/
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isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
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while (isa_dn && isa_dn != dn)
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isa_dn = isa_dn->parent;
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if (isa_dn_orig)
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of_node_put(isa_dn_orig);
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/* Count number of direct PCI children of the PHB. */
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for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
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children++;
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DBG("Children: %d\n", children);
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/* Calculate amount of DMA window per slot. Each window must be
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* a power of two (due to pci_alloc_consistent requirements).
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*
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* Keep 256MB aside for PHBs with ISA.
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*/
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if (!isa_dn) {
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/* No ISA/IDE - just set window size and return */
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pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
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while (pci->phb->dma_window_size * children > 0x80000000ul)
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pci->phb->dma_window_size >>= 1;
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DBG("No ISA/IDE, window size is 0x%lx\n",
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pci->phb->dma_window_size);
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pci->phb->dma_window_base_cur = 0;
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return;
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}
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/* If we have ISA, then we probably have an IDE
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* controller too. Allocate a 128MB table but
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* skip the first 128MB to avoid stepping on ISA
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* space.
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*/
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pci->phb->dma_window_size = 0x8000000ul;
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pci->phb->dma_window_base_cur = 0x8000000ul;
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tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
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pci->phb->node);
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iommu_table_setparms(pci->phb, dn, tbl);
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pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
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/* Divide the rest (1.75GB) among the children */
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pci->phb->dma_window_size = 0x80000000ul;
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while (pci->phb->dma_window_size * children > 0x70000000ul)
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pci->phb->dma_window_size >>= 1;
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DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size);
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}
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static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
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{
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struct iommu_table *tbl;
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struct device_node *dn, *pdn;
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struct pci_dn *ppci;
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const void *dma_window = NULL;
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dn = pci_bus_to_OF_node(bus);
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DBG("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", dn->full_name);
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/* Find nearest ibm,dma-window, walking up the device tree */
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for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
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dma_window = get_property(pdn, "ibm,dma-window", NULL);
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if (dma_window != NULL)
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break;
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}
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if (dma_window == NULL) {
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DBG(" no ibm,dma-window property !\n");
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return;
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}
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ppci = PCI_DN(pdn);
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DBG(" parent is %s, iommu_table: 0x%p\n",
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pdn->full_name, ppci->iommu_table);
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if (!ppci->iommu_table) {
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/* Bussubno hasn't been copied yet.
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* Do it now because iommu_table_setparms_lpar needs it.
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*/
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ppci->bussubno = bus->number;
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tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
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ppci->phb->node);
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iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
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ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
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DBG(" created table: %p\n", ppci->iommu_table);
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}
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if (pdn != dn)
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PCI_DN(dn)->iommu_table = ppci->iommu_table;
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}
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static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
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{
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struct device_node *dn;
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struct iommu_table *tbl;
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DBG("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
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dn = dev->dev.archdata.of_node;
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/* If we're the direct child of a root bus, then we need to allocate
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* an iommu table ourselves. The bus setup code should have setup
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* the window sizes already.
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*/
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if (!dev->bus->self) {
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struct pci_controller *phb = PCI_DN(dn)->phb;
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DBG(" --> first child, no bridge. Allocating iommu table.\n");
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tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
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phb->node);
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iommu_table_setparms(phb, dn, tbl);
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dev->dev.archdata.dma_data = iommu_init_table(tbl, phb->node);
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return;
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}
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/* If this device is further down the bus tree, search upwards until
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* an already allocated iommu table is found and use that.
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*/
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while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
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dn = dn->parent;
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if (dn && PCI_DN(dn))
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dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table;
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else
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printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
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pci_name(dev));
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}
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|
|
|
static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
|
|
{
|
|
int err = NOTIFY_OK;
|
|
struct device_node *np = node;
|
|
struct pci_dn *pci = PCI_DN(np);
|
|
|
|
switch (action) {
|
|
case PSERIES_RECONFIG_REMOVE:
|
|
if (pci && pci->iommu_table &&
|
|
get_property(np, "ibm,dma-window", NULL))
|
|
iommu_free_table(np);
|
|
break;
|
|
default:
|
|
err = NOTIFY_DONE;
|
|
break;
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static struct notifier_block iommu_reconfig_nb = {
|
|
.notifier_call = iommu_reconfig_notifier,
|
|
};
|
|
|
|
static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
|
|
{
|
|
struct device_node *pdn, *dn;
|
|
struct iommu_table *tbl;
|
|
const void *dma_window = NULL;
|
|
struct pci_dn *pci;
|
|
|
|
DBG("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
|
|
|
|
/* dev setup for LPAR is a little tricky, since the device tree might
|
|
* contain the dma-window properties per-device and not neccesarily
|
|
* for the bus. So we need to search upwards in the tree until we
|
|
* either hit a dma-window property, OR find a parent with a table
|
|
* already allocated.
|
|
*/
|
|
dn = pci_device_to_OF_node(dev);
|
|
DBG(" node is %s\n", dn->full_name);
|
|
|
|
for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
|
|
pdn = pdn->parent) {
|
|
dma_window = get_property(pdn, "ibm,dma-window", NULL);
|
|
if (dma_window)
|
|
break;
|
|
}
|
|
|
|
DBG(" parent is %s\n", pdn->full_name);
|
|
|
|
/* Check for parent == NULL so we don't try to setup the empty EADS
|
|
* slots on POWER4 machines.
|
|
*/
|
|
if (dma_window == NULL || pdn->parent == NULL) {
|
|
DBG(" no dma window for device, linking to parent\n");
|
|
dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table;
|
|
return;
|
|
}
|
|
DBG(" found DMA window, table: %p\n", pci->iommu_table);
|
|
|
|
pci = PCI_DN(pdn);
|
|
if (!pci->iommu_table) {
|
|
/* iommu_table_setparms_lpar needs bussubno. */
|
|
pci->bussubno = pci->phb->bus->number;
|
|
|
|
tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
|
|
pci->phb->node);
|
|
|
|
iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
|
|
|
|
pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
|
|
DBG(" created table: %p\n", pci->iommu_table);
|
|
}
|
|
|
|
dev->dev.archdata.dma_data = pci->iommu_table;
|
|
}
|
|
|
|
/* These are called very early. */
|
|
void iommu_init_early_pSeries(void)
|
|
{
|
|
if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) {
|
|
/* Direct I/O, IOMMU off */
|
|
ppc_md.pci_dma_dev_setup = NULL;
|
|
ppc_md.pci_dma_bus_setup = NULL;
|
|
pci_dma_ops = &dma_direct_ops;
|
|
return;
|
|
}
|
|
|
|
if (firmware_has_feature(FW_FEATURE_LPAR)) {
|
|
if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
|
|
ppc_md.tce_build = tce_buildmulti_pSeriesLP;
|
|
ppc_md.tce_free = tce_freemulti_pSeriesLP;
|
|
} else {
|
|
ppc_md.tce_build = tce_build_pSeriesLP;
|
|
ppc_md.tce_free = tce_free_pSeriesLP;
|
|
}
|
|
ppc_md.tce_get = tce_get_pSeriesLP;
|
|
ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
|
|
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
|
|
} else {
|
|
ppc_md.tce_build = tce_build_pSeries;
|
|
ppc_md.tce_free = tce_free_pSeries;
|
|
ppc_md.tce_get = tce_get_pseries;
|
|
ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
|
|
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
|
|
}
|
|
|
|
|
|
pSeries_reconfig_notifier_register(&iommu_reconfig_nb);
|
|
|
|
pci_dma_ops = &dma_iommu_ops;
|
|
}
|
|
|