![Antonino A. Daplas](/assets/img/avatar_default.png)
Use Read/WriteCrtc() to access CRTC registers in nv_i2c.c. These are safer because it uses the correct CRTC base (0x3bx or 0x3dx). Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
170 lines
3.6 KiB
C
170 lines
3.6 KiB
C
/*
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* linux/drivers/video/nvidia/nvidia-i2c.c - nVidia i2c
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*
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* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
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*
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* Based on rivafb-i2c.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/fb.h>
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#include <asm/io.h>
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#include "nv_type.h"
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#include "nv_local.h"
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#include "nv_proto.h"
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#include "../edid.h"
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static void nvidia_gpio_setscl(void *data, int state)
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{
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struct nvidia_i2c_chan *chan = data;
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struct nvidia_par *par = chan->par;
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u32 val;
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val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
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if (state)
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val |= 0x20;
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else
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val &= ~0x20;
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NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
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}
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static void nvidia_gpio_setsda(void *data, int state)
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{
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struct nvidia_i2c_chan *chan = data;
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struct nvidia_par *par = chan->par;
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u32 val;
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val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
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if (state)
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val |= 0x10;
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else
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val &= ~0x10;
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NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
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}
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static int nvidia_gpio_getscl(void *data)
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{
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struct nvidia_i2c_chan *chan = data;
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struct nvidia_par *par = chan->par;
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u32 val = 0;
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if (NVReadCrtc(par, chan->ddc_base) & 0x04)
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val = 1;
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return val;
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}
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static int nvidia_gpio_getsda(void *data)
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{
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struct nvidia_i2c_chan *chan = data;
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struct nvidia_par *par = chan->par;
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u32 val = 0;
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if (NVReadCrtc(par, chan->ddc_base) & 0x08)
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val = 1;
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return val;
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}
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static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name,
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unsigned int i2c_class)
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{
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int rc;
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strcpy(chan->adapter.name, name);
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chan->adapter.owner = THIS_MODULE;
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chan->adapter.id = I2C_HW_B_NVIDIA;
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chan->adapter.class = i2c_class;
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chan->adapter.algo_data = &chan->algo;
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chan->adapter.dev.parent = &chan->par->pci_dev->dev;
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chan->algo.setsda = nvidia_gpio_setsda;
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chan->algo.setscl = nvidia_gpio_setscl;
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chan->algo.getsda = nvidia_gpio_getsda;
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chan->algo.getscl = nvidia_gpio_getscl;
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chan->algo.udelay = 40;
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chan->algo.timeout = msecs_to_jiffies(2);
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chan->algo.data = chan;
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i2c_set_adapdata(&chan->adapter, chan);
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/* Raise SCL and SDA */
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nvidia_gpio_setsda(chan, 1);
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nvidia_gpio_setscl(chan, 1);
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udelay(20);
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rc = i2c_bit_add_bus(&chan->adapter);
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if (rc == 0)
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dev_dbg(&chan->par->pci_dev->dev,
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"I2C bus %s registered.\n", name);
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else {
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dev_warn(&chan->par->pci_dev->dev,
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"Failed to register I2C bus %s.\n", name);
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chan->par = NULL;
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}
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return rc;
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}
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void nvidia_create_i2c_busses(struct nvidia_par *par)
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{
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par->chan[0].par = par;
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par->chan[1].par = par;
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par->chan[2].par = par;
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par->chan[0].ddc_base = 0x36;
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nvidia_setup_i2c_bus(&par->chan[0], "nvidia #0", I2C_CLASS_HWMON);
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par->chan[1].ddc_base = 0x3e;
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nvidia_setup_i2c_bus(&par->chan[1], "nvidia #1", 0);
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par->chan[2].ddc_base = 0x50;
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nvidia_setup_i2c_bus(&par->chan[2], "nvidia #2", 0);
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}
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void nvidia_delete_i2c_busses(struct nvidia_par *par)
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{
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int i;
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for (i = 0; i < 3; i++) {
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if (!par->chan[i].par)
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continue;
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i2c_del_adapter(&par->chan[i].adapter);
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par->chan[i].par = NULL;
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}
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}
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int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid)
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{
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struct nvidia_par *par = info->par;
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u8 *edid = NULL;
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if (par->chan[conn - 1].par)
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edid = fb_ddc_read(&par->chan[conn - 1].adapter);
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if (!edid && conn == 1) {
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/* try to get from firmware */
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const u8 *e = fb_firmware_edid(info->device);
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if (e != NULL)
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edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
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}
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*out_edid = edid;
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return (edid) ? 0 : 1;
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}
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