![Antonino A. Daplas](/assets/img/avatar_default.png)
Add proper support for the Geforce 7600 (device id 0x039x). This also sync's nvidiafb with the latest Xorg nv driver. Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
675 lines
18 KiB
C
675 lines
18 KiB
C
/***************************************************************************\
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|* *|
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|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
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|* *|
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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|* international laws. Users and possessors of this source code are *|
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|* hereby granted a nonexclusive, royalty-free copyright license to *|
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|* use this code in individual and commercial software. *|
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|* *|
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|* Any use of this source code must include, in the user documenta- *|
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|* tion and internal comments to the code, notices to the end user *|
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|* as follows: *|
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|* *|
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|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
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|* *|
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|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
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|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
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|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
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|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
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|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
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|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
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|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
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|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
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|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
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|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
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|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
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|* *|
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|* U.S. Government End Users. This source code is a "commercial *|
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|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
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|* consisting of "commercial computer software" and "commercial *|
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|* computer software documentation," as such terms are used in *|
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|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
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|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
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|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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|* all U.S. Government End Users acquire the source code with only *|
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|* those rights set forth herein. *|
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|* *|
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\***************************************************************************/
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/*
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* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
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* XFree86 'nv' driver, this source code is provided under MIT-style licensing
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* where the source code is provided "as is" without warranty of any kind.
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* The only usage restriction is for the copyright notices to be retained
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* whenever code is used.
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*
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* Antonino Daplas <adaplas@pol.net> 2005-03-11
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*/
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#include <video/vga.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include "nv_type.h"
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#include "nv_local.h"
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#include "nv_proto.h"
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/*
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* Override VGA I/O routines.
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*/
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void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
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{
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VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
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VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
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}
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u8 NVReadCrtc(struct nvidia_par *par, u8 index)
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{
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VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
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return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
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}
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void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
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{
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VGA_WR08(par->PVIO, VGA_GFX_I, index);
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VGA_WR08(par->PVIO, VGA_GFX_D, value);
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}
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u8 NVReadGr(struct nvidia_par *par, u8 index)
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{
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VGA_WR08(par->PVIO, VGA_GFX_I, index);
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return (VGA_RD08(par->PVIO, VGA_GFX_D));
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}
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void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
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{
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VGA_WR08(par->PVIO, VGA_SEQ_I, index);
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VGA_WR08(par->PVIO, VGA_SEQ_D, value);
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}
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u8 NVReadSeq(struct nvidia_par *par, u8 index)
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{
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VGA_WR08(par->PVIO, VGA_SEQ_I, index);
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return (VGA_RD08(par->PVIO, VGA_SEQ_D));
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}
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void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
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{
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volatile u8 tmp;
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tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
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if (par->paletteEnabled)
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index &= ~0x20;
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else
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index |= 0x20;
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VGA_WR08(par->PCIO, VGA_ATT_IW, index);
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VGA_WR08(par->PCIO, VGA_ATT_W, value);
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}
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u8 NVReadAttr(struct nvidia_par *par, u8 index)
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{
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volatile u8 tmp;
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tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
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if (par->paletteEnabled)
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index &= ~0x20;
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else
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index |= 0x20;
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VGA_WR08(par->PCIO, VGA_ATT_IW, index);
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return (VGA_RD08(par->PCIO, VGA_ATT_R));
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}
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void NVWriteMiscOut(struct nvidia_par *par, u8 value)
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{
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VGA_WR08(par->PVIO, VGA_MIS_W, value);
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}
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u8 NVReadMiscOut(struct nvidia_par *par)
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{
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return (VGA_RD08(par->PVIO, VGA_MIS_R));
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}
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#if 0
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void NVEnablePalette(struct nvidia_par *par)
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{
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volatile u8 tmp;
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tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
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VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
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par->paletteEnabled = 1;
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}
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void NVDisablePalette(struct nvidia_par *par)
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{
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volatile u8 tmp;
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tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
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VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
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par->paletteEnabled = 0;
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}
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#endif /* 0 */
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void NVWriteDacMask(struct nvidia_par *par, u8 value)
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{
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VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
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}
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#if 0
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u8 NVReadDacMask(struct nvidia_par *par)
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{
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return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
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}
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#endif /* 0 */
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void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
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{
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VGA_WR08(par->PDIO, VGA_PEL_IR, value);
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}
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void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
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{
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VGA_WR08(par->PDIO, VGA_PEL_IW, value);
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}
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void NVWriteDacData(struct nvidia_par *par, u8 value)
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{
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VGA_WR08(par->PDIO, VGA_PEL_D, value);
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}
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u8 NVReadDacData(struct nvidia_par *par)
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{
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return (VGA_RD08(par->PDIO, VGA_PEL_D));
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}
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static int NVIsConnected(struct nvidia_par *par, int output)
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{
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volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
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u32 reg52C, reg608, dac0_reg608 = 0;
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int present;
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if (output) {
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dac0_reg608 = NV_RD32(PRAMDAC, 0x0608);
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PRAMDAC += 0x800;
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}
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reg52C = NV_RD32(PRAMDAC, 0x052C);
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reg608 = NV_RD32(PRAMDAC, 0x0608);
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NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
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NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
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msleep(1);
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NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
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NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
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NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
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0x00001000);
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msleep(1);
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present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
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if (present)
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printk("nvidiafb: CRTC%i analog found\n", output);
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else
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printk("nvidiafb: CRTC%i analog not found\n", output);
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if (output)
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NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
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NV_WR32(PRAMDAC, 0x052C, reg52C);
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NV_WR32(PRAMDAC, 0x0608, reg608);
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return present;
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}
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static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
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{
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if (head) {
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par->PCIO = par->PCIO0 + 0x2000;
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par->PCRTC = par->PCRTC0 + 0x800;
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par->PRAMDAC = par->PRAMDAC0 + 0x800;
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par->PDIO = par->PDIO0 + 0x2000;
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} else {
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par->PCIO = par->PCIO0;
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par->PCRTC = par->PCRTC0;
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par->PRAMDAC = par->PRAMDAC0;
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par->PDIO = par->PDIO0;
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}
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}
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static void nv4GetConfig(struct nvidia_par *par)
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{
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if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
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par->RamAmountKBytes =
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((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
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1024 * 2;
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} else {
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switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
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case 0:
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par->RamAmountKBytes = 1024 * 32;
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break;
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case 1:
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par->RamAmountKBytes = 1024 * 4;
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break;
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case 2:
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par->RamAmountKBytes = 1024 * 8;
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break;
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case 3:
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default:
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par->RamAmountKBytes = 1024 * 16;
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break;
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}
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}
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par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
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14318 : 13500;
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par->CURSOR = &par->PRAMIN[0x1E00];
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par->MinVClockFreqKHz = 12000;
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par->MaxVClockFreqKHz = 350000;
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}
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static void nv10GetConfig(struct nvidia_par *par)
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{
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struct pci_dev *dev;
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u32 implementation = par->Chipset & 0x0ff0;
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#ifdef __BIG_ENDIAN
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/* turn on big endian register access */
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if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
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NV_WR32(par->PMC, 0x0004, 0x01000001);
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mb();
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}
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#endif
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dev = pci_get_bus_and_slot(0, 1);
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if ((par->Chipset & 0xffff) == 0x01a0) {
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int amt = 0;
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pci_read_config_dword(dev, 0x7c, &amt);
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par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
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} else if ((par->Chipset & 0xffff) == 0x01f0) {
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int amt = 0;
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pci_read_config_dword(dev, 0x84, &amt);
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par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
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} else {
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par->RamAmountKBytes =
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(NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
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}
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pci_dev_put(dev);
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par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
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14318 : 13500;
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if (par->twoHeads && (implementation != 0x0110)) {
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if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
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par->CrystalFreqKHz = 27000;
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}
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par->CURSOR = NULL; /* can't set this here */
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par->MinVClockFreqKHz = 12000;
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par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
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}
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int NVCommonSetup(struct fb_info *info)
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{
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struct nvidia_par *par = info->par;
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struct fb_var_screeninfo *var;
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u16 implementation = par->Chipset & 0x0ff0;
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u8 *edidA = NULL, *edidB = NULL;
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struct fb_monspecs *monitorA, *monitorB;
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struct fb_monspecs *monA = NULL, *monB = NULL;
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int mobile = 0;
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int tvA = 0;
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int tvB = 0;
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int FlatPanel = -1; /* really means the CRTC is slaved */
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int Television = 0;
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int err = 0;
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var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
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monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
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monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
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if (!var || !monitorA || !monitorB) {
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err = -ENOMEM;
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goto done;
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}
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par->PRAMIN = par->REGS + (0x00710000 / 4);
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par->PCRTC0 = par->REGS + (0x00600000 / 4);
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par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
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par->PFB = par->REGS + (0x00100000 / 4);
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par->PFIFO = par->REGS + (0x00002000 / 4);
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par->PGRAPH = par->REGS + (0x00400000 / 4);
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par->PEXTDEV = par->REGS + (0x00101000 / 4);
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par->PTIMER = par->REGS + (0x00009000 / 4);
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par->PMC = par->REGS + (0x00000000 / 4);
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par->FIFO = par->REGS + (0x00800000 / 4);
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/* 8 bit registers */
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par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
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par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
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par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
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par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
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(implementation != 0x0100) &&
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(implementation != 0x0150) &&
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(implementation != 0x01A0) && (implementation != 0x0200);
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par->fpScaler = (par->FpScale && par->twoHeads &&
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(implementation != 0x0110));
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par->twoStagePLL = (implementation == 0x0310) ||
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(implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
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par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
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(implementation != 0x0100);
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par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
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/* look for known laptop chips */
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switch (par->Chipset & 0xffff) {
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case 0x0112:
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case 0x0174:
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case 0x0175:
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case 0x0176:
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case 0x0177:
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case 0x0179:
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case 0x017C:
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case 0x017D:
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case 0x0186:
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case 0x0187:
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case 0x018D:
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case 0x0228:
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case 0x0286:
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case 0x028C:
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case 0x0316:
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case 0x0317:
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case 0x031A:
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case 0x031B:
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case 0x031C:
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case 0x031D:
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case 0x031E:
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case 0x031F:
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case 0x0324:
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case 0x0325:
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case 0x0328:
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case 0x0329:
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case 0x032C:
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case 0x032D:
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case 0x0347:
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case 0x0348:
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case 0x0349:
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case 0x034B:
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case 0x034C:
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case 0x0160:
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case 0x0166:
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case 0x0169:
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case 0x016B:
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case 0x016C:
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case 0x016D:
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case 0x00C8:
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case 0x00CC:
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case 0x0144:
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case 0x0146:
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case 0x0147:
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case 0x0148:
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case 0x0098:
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case 0x0099:
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mobile = 1;
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break;
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default:
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break;
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}
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if (par->Architecture == NV_ARCH_04)
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nv4GetConfig(par);
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else
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nv10GetConfig(par);
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NVSelectHeadRegisters(par, 0);
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NVLockUnlock(par, 0);
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par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
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par->Television = 0;
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nvidia_create_i2c_busses(par);
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if (!par->twoHeads) {
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par->CRTCnumber = 0;
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if (nvidia_probe_i2c_connector(info, 1, &edidA))
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nvidia_probe_of_connector(info, 1, &edidA);
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if (edidA && !fb_parse_edid(edidA, var)) {
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printk("nvidiafb: EDID found from BUS1\n");
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monA = monitorA;
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fb_edid_to_monspecs(edidA, monA);
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FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
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/* NV4 doesn't support FlatPanels */
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if ((par->Chipset & 0x0fff) <= 0x0020)
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FlatPanel = 0;
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} else {
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VGA_WR08(par->PCIO, 0x03D4, 0x28);
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if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
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VGA_WR08(par->PCIO, 0x03D4, 0x33);
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if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
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Television = 1;
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FlatPanel = 1;
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} else {
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FlatPanel = 0;
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}
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printk("nvidiafb: HW is currently programmed for %s\n",
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FlatPanel ? (Television ? "TV" : "DFP") :
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"CRT");
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}
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if (par->FlatPanel == -1) {
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par->FlatPanel = FlatPanel;
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par->Television = Television;
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} else {
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printk("nvidiafb: Forcing display type to %s as "
|
|
"specified\n", par->FlatPanel ? "DFP" : "CRT");
|
|
}
|
|
} else {
|
|
u8 outputAfromCRTC, outputBfromCRTC;
|
|
int CRTCnumber = -1;
|
|
u8 slaved_on_A, slaved_on_B;
|
|
int analog_on_A, analog_on_B;
|
|
u32 oldhead;
|
|
u8 cr44;
|
|
|
|
if (implementation != 0x0110) {
|
|
if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
|
|
outputAfromCRTC = 1;
|
|
else
|
|
outputAfromCRTC = 0;
|
|
if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
|
|
outputBfromCRTC = 1;
|
|
else
|
|
outputBfromCRTC = 0;
|
|
analog_on_A = NVIsConnected(par, 0);
|
|
analog_on_B = NVIsConnected(par, 1);
|
|
} else {
|
|
outputAfromCRTC = 0;
|
|
outputBfromCRTC = 1;
|
|
analog_on_A = 0;
|
|
analog_on_B = 0;
|
|
}
|
|
|
|
VGA_WR08(par->PCIO, 0x03D4, 0x44);
|
|
cr44 = VGA_RD08(par->PCIO, 0x03D5);
|
|
|
|
VGA_WR08(par->PCIO, 0x03D5, 3);
|
|
NVSelectHeadRegisters(par, 1);
|
|
NVLockUnlock(par, 0);
|
|
|
|
VGA_WR08(par->PCIO, 0x03D4, 0x28);
|
|
slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
|
|
if (slaved_on_B) {
|
|
VGA_WR08(par->PCIO, 0x03D4, 0x33);
|
|
tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
|
|
}
|
|
|
|
VGA_WR08(par->PCIO, 0x03D4, 0x44);
|
|
VGA_WR08(par->PCIO, 0x03D5, 0);
|
|
NVSelectHeadRegisters(par, 0);
|
|
NVLockUnlock(par, 0);
|
|
|
|
VGA_WR08(par->PCIO, 0x03D4, 0x28);
|
|
slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
|
|
if (slaved_on_A) {
|
|
VGA_WR08(par->PCIO, 0x03D4, 0x33);
|
|
tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
|
|
}
|
|
|
|
oldhead = NV_RD32(par->PCRTC0, 0x00000860);
|
|
NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
|
|
|
|
if (nvidia_probe_i2c_connector(info, 1, &edidA))
|
|
nvidia_probe_of_connector(info, 1, &edidA);
|
|
if (edidA && !fb_parse_edid(edidA, var)) {
|
|
printk("nvidiafb: EDID found from BUS1\n");
|
|
monA = monitorA;
|
|
fb_edid_to_monspecs(edidA, monA);
|
|
}
|
|
|
|
if (nvidia_probe_i2c_connector(info, 2, &edidB))
|
|
nvidia_probe_of_connector(info, 2, &edidB);
|
|
if (edidB && !fb_parse_edid(edidB, var)) {
|
|
printk("nvidiafb: EDID found from BUS2\n");
|
|
monB = monitorB;
|
|
fb_edid_to_monspecs(edidB, monB);
|
|
}
|
|
|
|
if (slaved_on_A && !tvA) {
|
|
CRTCnumber = 0;
|
|
FlatPanel = 1;
|
|
printk("nvidiafb: CRTC 0 is currently programmed for "
|
|
"DFP\n");
|
|
} else if (slaved_on_B && !tvB) {
|
|
CRTCnumber = 1;
|
|
FlatPanel = 1;
|
|
printk("nvidiafb: CRTC 1 is currently programmed "
|
|
"for DFP\n");
|
|
} else if (analog_on_A) {
|
|
CRTCnumber = outputAfromCRTC;
|
|
FlatPanel = 0;
|
|
printk("nvidiafb: CRTC %i appears to have a "
|
|
"CRT attached\n", CRTCnumber);
|
|
} else if (analog_on_B) {
|
|
CRTCnumber = outputBfromCRTC;
|
|
FlatPanel = 0;
|
|
printk("nvidiafb: CRTC %i"
|
|
"appears to have a "
|
|
"CRT attached\n", CRTCnumber);
|
|
} else if (slaved_on_A) {
|
|
CRTCnumber = 0;
|
|
FlatPanel = 1;
|
|
Television = 1;
|
|
printk("nvidiafb: CRTC 0 is currently programmed "
|
|
"for TV\n");
|
|
} else if (slaved_on_B) {
|
|
CRTCnumber = 1;
|
|
FlatPanel = 1;
|
|
Television = 1;
|
|
printk("nvidiafb: CRTC 1 is currently programmed for "
|
|
"TV\n");
|
|
} else if (monA) {
|
|
FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
|
|
} else if (monB) {
|
|
FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
|
|
}
|
|
|
|
if (par->FlatPanel == -1) {
|
|
if (FlatPanel != -1) {
|
|
par->FlatPanel = FlatPanel;
|
|
par->Television = Television;
|
|
} else {
|
|
printk("nvidiafb: Unable to detect display "
|
|
"type...\n");
|
|
if (mobile) {
|
|
printk("...On a laptop, assuming "
|
|
"DFP\n");
|
|
par->FlatPanel = 1;
|
|
} else {
|
|
printk("...Using default of CRT\n");
|
|
par->FlatPanel = 0;
|
|
}
|
|
}
|
|
} else {
|
|
printk("nvidiafb: Forcing display type to %s as "
|
|
"specified\n", par->FlatPanel ? "DFP" : "CRT");
|
|
}
|
|
|
|
if (par->CRTCnumber == -1) {
|
|
if (CRTCnumber != -1)
|
|
par->CRTCnumber = CRTCnumber;
|
|
else {
|
|
printk("nvidiafb: Unable to detect which "
|
|
"CRTCNumber...\n");
|
|
if (par->FlatPanel)
|
|
par->CRTCnumber = 1;
|
|
else
|
|
par->CRTCnumber = 0;
|
|
printk("...Defaulting to CRTCNumber %i\n",
|
|
par->CRTCnumber);
|
|
}
|
|
} else {
|
|
printk("nvidiafb: Forcing CRTCNumber %i as "
|
|
"specified\n", par->CRTCnumber);
|
|
}
|
|
|
|
if (monA) {
|
|
if (((monA->input & FB_DISP_DDI) &&
|
|
par->FlatPanel) ||
|
|
((!(monA->input & FB_DISP_DDI)) &&
|
|
!par->FlatPanel)) {
|
|
if (monB) {
|
|
fb_destroy_modedb(monB->modedb);
|
|
monB = NULL;
|
|
}
|
|
} else {
|
|
fb_destroy_modedb(monA->modedb);
|
|
monA = NULL;
|
|
}
|
|
}
|
|
|
|
if (monB) {
|
|
if (((monB->input & FB_DISP_DDI) &&
|
|
!par->FlatPanel) ||
|
|
((!(monB->input & FB_DISP_DDI)) &&
|
|
par->FlatPanel)) {
|
|
fb_destroy_modedb(monB->modedb);
|
|
monB = NULL;
|
|
} else
|
|
monA = monB;
|
|
}
|
|
|
|
if (implementation == 0x0110)
|
|
cr44 = par->CRTCnumber * 0x3;
|
|
|
|
NV_WR32(par->PCRTC0, 0x00000860, oldhead);
|
|
|
|
VGA_WR08(par->PCIO, 0x03D4, 0x44);
|
|
VGA_WR08(par->PCIO, 0x03D5, cr44);
|
|
NVSelectHeadRegisters(par, par->CRTCnumber);
|
|
}
|
|
|
|
printk("nvidiafb: Using %s on CRTC %i\n",
|
|
par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
|
|
par->CRTCnumber);
|
|
|
|
if (par->FlatPanel && !par->Television) {
|
|
par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
|
|
par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
|
|
par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
|
|
|
|
printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
|
|
}
|
|
|
|
if (monA)
|
|
info->monspecs = *monA;
|
|
|
|
if (!par->FlatPanel || !par->twoHeads)
|
|
par->FPDither = 0;
|
|
|
|
par->LVDS = 0;
|
|
if (par->FlatPanel && par->twoHeads) {
|
|
NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
|
|
if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
|
|
par->LVDS = 1;
|
|
printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");
|
|
}
|
|
|
|
kfree(edidA);
|
|
kfree(edidB);
|
|
done:
|
|
kfree(var);
|
|
kfree(monitorA);
|
|
kfree(monitorB);
|
|
return err;
|
|
}
|