![Linus Torvalds](/assets/img/avatar_default.png)
Here is a collection of cleanup patches. Among the pieces that stand out are: - The deletion of h720x platforms - Split of at91 non-dt platforms to their own Kconfig file to keep them separate - General cleanups and refactoring of i.MX and MXS platforms - Some restructuring of clock tables for OMAP - Convertion of PMC driver for Tegra to dt-only - Some renames of sunxi -> sun4i (Allwinner A10) - ... plus a bunch of other stuff that I haven't mentioned -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRggUqAAoJEIwa5zzehBx3HjEQAJwp7heRs/HwTDzmzcyHkRMV usbaa9dHBuAZ0DzsWjLK99xEn8VWD9TvbeP6hN5gNhxko06UVza3o8PI2iV1ztMB 9K3u2+LS5on/5cOxnsU1va16h5hBZ0ZIgNx5NY+PZ5mBY6v1U3qTjljPP62iXp63 w+sdXeZDe/c5JvuoDRbY0OBR++3Jp8cQg7KbU78jWz3r5D2rC1zwhkf2audcRY6b jIWTj9M8CHynh/D6OzKqDcOYorBHNSRj0YbiWS2nnMfm+0V8nya00EPRpCPRiBUb sobSy1CI9Qxiih3bOf6QCfzCRzJ5hbtE0zlI8g3bqtEZ1yOsE949HrKapWHJJdIU JNTXrxXORAnaRhbzvSPNpp/iJBSDQRsfEETgv5BuHg/4lzTQfzElySbcgb4EeoHr 7Zt8ZR2/Du+u76qIPqs19ES3Wx+nOEOfSDAgZmlfPvlwmlGDYvqAXoeJ006VXnhG JacLuD/cFnJ1w00Bcl48ZXMIsVkoRqjvsCG5q688HGXMM1lU8DfgUpQY6OCWAbdu kFnBinJZk+HbE8FGS8O0BoQ+oiC0YIr2XhATL66PGHq7bLHb5ycwvZ7mrfC0AN9j M9hqTFednwfo9wF8vSj5nMsxXwP8/mky4ECGoFvLsMYDosunrNVnAHtTgDSE+ZgO 6kQJ1P8jBBXn2LyjF88W =xCAx -----END PGP SIGNATURE----- Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanup from Olof Johansson: "Here is a collection of cleanup patches. Among the pieces that stand out are: - The deletion of h720x platforms - Split of at91 non-dt platforms to their own Kconfig file to keep them separate - General cleanups and refactoring of i.MX and MXS platforms - Some restructuring of clock tables for OMAP - Convertion of PMC driver for Tegra to dt-only - Some renames of sunxi -> sun4i (Allwinner A10) - ... plus a bunch of other stuff that I haven't mentioned" * tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits) ARM: i.MX: remove unused ARCH_* configs ARM i.MX53: remove platform ahci support ARM: sunxi: Rework the restart code irqchip: sunxi: Rename sunxi to sun4i irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro clocksource: sunxi: Rename sunxi to sun4i clocksource: sunxi: make use of CLKSRC_OF clocksource: sunxi: Cleanup the timer code ARM: at91: remove trailing semicolon from macros ARM: at91/setup: fix trivial typos ARM: EXYNOS: remove "config EXYNOS_DEV_DRM" ARM: EXYNOS: change the name of USB ohci header ARM: SAMSUNG: Remove unnecessary code for dma ARM: S3C24XX: Remove unused GPIO drive strength register definitions ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2412 ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2410 ARM: S3C24XX: Removed unneeded dependency on ARCH_S3C24XX for boards ARM: SAMSUNG: Fix typo "CONFIG_SAMSUNG_DEV_RTC" ARM: S5P64X0: Fix typo "CONFIG_S5P64X0_SETUP_SDHCI" ...
218 lines
5.4 KiB
C
218 lines
5.4 KiB
C
/*
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* OMAP4+ CPU idle Routines
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*
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* Copyright (C) 2011-2013 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/export.h>
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#include <asm/cpuidle.h>
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#include <asm/proc-fns.h>
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#include "common.h"
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#include "pm.h"
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#include "prm.h"
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#include "clockdomain.h"
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/* Machine specific information */
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struct idle_statedata {
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u32 cpu_state;
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u32 mpu_logic_state;
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u32 mpu_state;
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};
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static struct idle_statedata omap4_idle_data[] = {
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{
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.cpu_state = PWRDM_POWER_ON,
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.mpu_state = PWRDM_POWER_ON,
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.mpu_logic_state = PWRDM_POWER_RET,
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},
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{
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.cpu_state = PWRDM_POWER_OFF,
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.mpu_state = PWRDM_POWER_RET,
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.mpu_logic_state = PWRDM_POWER_RET,
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},
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{
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.cpu_state = PWRDM_POWER_OFF,
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.mpu_state = PWRDM_POWER_RET,
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.mpu_logic_state = PWRDM_POWER_OFF,
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},
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};
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static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
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static struct clockdomain *cpu_clkdm[NR_CPUS];
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static atomic_t abort_barrier;
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static bool cpu_done[NR_CPUS];
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static struct idle_statedata *state_ptr = &omap4_idle_data[0];
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/* Private functions */
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/**
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* omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions
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* @dev: cpuidle device
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* @drv: cpuidle driver
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* @index: the index of state to be entered
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*
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* Called from the CPUidle framework to program the device to the
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* specified low power state selected by the governor.
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* Returns the amount of time spent in the low power state.
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*/
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static int omap_enter_idle_simple(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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omap_do_wfi();
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return index;
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}
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static int omap_enter_idle_coupled(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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struct idle_statedata *cx = state_ptr + index;
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/*
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* CPU0 has to wait and stay ON until CPU1 is OFF state.
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* This is necessary to honour hardware recommondation
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* of triggeing all the possible low power modes once CPU1 is
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* out of coherency and in OFF mode.
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*/
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if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
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while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
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cpu_relax();
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/*
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* CPU1 could have already entered & exited idle
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* without hitting off because of a wakeup
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* or a failed attempt to hit off mode. Check for
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* that here, otherwise we could spin forever
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* waiting for CPU1 off.
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*/
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if (cpu_done[1])
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goto fail;
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}
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}
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/*
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* Call idle CPU PM enter notifier chain so that
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* VFP and per CPU interrupt context is saved.
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*/
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cpu_pm_enter();
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if (dev->cpu == 0) {
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pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
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omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
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/*
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* Call idle CPU cluster PM enter notifier chain
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* to save GIC and wakeupgen context.
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*/
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if ((cx->mpu_state == PWRDM_POWER_RET) &&
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(cx->mpu_logic_state == PWRDM_POWER_OFF))
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cpu_cluster_pm_enter();
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}
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omap4_enter_lowpower(dev->cpu, cx->cpu_state);
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cpu_done[dev->cpu] = true;
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/* Wakeup CPU1 only if it is not offlined */
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if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
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clkdm_wakeup(cpu_clkdm[1]);
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omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
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clkdm_allow_idle(cpu_clkdm[1]);
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}
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/*
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* Call idle CPU PM exit notifier chain to restore
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* VFP and per CPU IRQ context.
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*/
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cpu_pm_exit();
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/*
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* Call idle CPU cluster PM exit notifier chain
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* to restore GIC and wakeupgen context.
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*/
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if ((cx->mpu_state == PWRDM_POWER_RET) &&
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(cx->mpu_logic_state == PWRDM_POWER_OFF))
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cpu_cluster_pm_exit();
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fail:
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cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
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cpu_done[dev->cpu] = false;
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return index;
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}
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static struct cpuidle_driver omap4_idle_driver = {
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.name = "omap4_idle",
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.owner = THIS_MODULE,
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.states = {
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{
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/* C1 - CPU0 ON + CPU1 ON + MPU ON */
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.exit_latency = 2 + 2,
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.target_residency = 5,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = omap_enter_idle_simple,
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.name = "C1",
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.desc = "CPUx ON, MPUSS ON"
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},
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{
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/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
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.exit_latency = 328 + 440,
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.target_residency = 960,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
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CPUIDLE_FLAG_TIMER_STOP,
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.enter = omap_enter_idle_coupled,
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.name = "C2",
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.desc = "CPUx OFF, MPUSS CSWR",
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},
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{
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/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
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.exit_latency = 460 + 518,
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.target_residency = 1100,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
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CPUIDLE_FLAG_TIMER_STOP,
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.enter = omap_enter_idle_coupled,
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.name = "C3",
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.desc = "CPUx OFF, MPUSS OSWR",
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},
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},
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.state_count = ARRAY_SIZE(omap4_idle_data),
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.safe_state_index = 0,
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};
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/* Public functions */
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/**
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* omap4_idle_init - Init routine for OMAP4+ idle
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*
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* Registers the OMAP4+ specific cpuidle driver to the cpuidle
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* framework with the valid set of states.
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*/
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int __init omap4_idle_init(void)
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{
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mpu_pd = pwrdm_lookup("mpu_pwrdm");
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cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
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cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
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if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
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return -ENODEV;
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cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
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cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
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if (!cpu_clkdm[0] || !cpu_clkdm[1])
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return -ENODEV;
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return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
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}
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