![Paul Gortmaker](/assets/img/avatar_default.png)
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0
("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
232 lines
5.6 KiB
C
232 lines
5.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
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* Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/smp.h>
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#include <asm/sn/arch.h>
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#include <asm/pci/bridge.h>
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#include <asm/paccess.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/sn0/hub.h>
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/*
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* Max #PCI busses we can handle; ie, max #PCI bridges.
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*/
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#define MAX_PCI_BUSSES 40
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/*
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* Max #PCI devices (like scsi controllers) we handle on a bus.
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*/
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#define MAX_DEVICES_PER_PCIBUS 8
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/*
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* XXX: No kmalloc available when we do our crosstalk scan,
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* we should try to move it later in the boot process.
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*/
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static struct bridge_controller bridges[MAX_PCI_BUSSES];
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/*
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* Translate from irq to software PCI bus number and PCI slot.
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*/
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struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
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int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
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extern struct pci_ops bridge_pci_ops;
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int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
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{
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unsigned long offset = NODE_OFFSET(nasid);
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struct bridge_controller *bc;
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static int num_bridges = 0;
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bridge_t *bridge;
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int slot;
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pci_set_flags(PCI_PROBE_ONLY);
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printk("a bridge\n");
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/* XXX: kludge alert.. */
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if (!num_bridges)
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ioport_resource.end = ~0UL;
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bc = &bridges[num_bridges];
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bc->pc.pci_ops = &bridge_pci_ops;
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bc->pc.mem_resource = &bc->mem;
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bc->pc.io_resource = &bc->io;
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bc->pc.index = num_bridges;
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bc->mem.name = "Bridge PCI MEM";
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bc->pc.mem_offset = offset;
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bc->mem.start = 0;
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bc->mem.end = ~0UL;
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bc->mem.flags = IORESOURCE_MEM;
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bc->io.name = "Bridge IO MEM";
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bc->pc.io_offset = offset;
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bc->io.start = 0UL;
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bc->io.end = ~0UL;
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bc->io.flags = IORESOURCE_IO;
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bc->irq_cpu = smp_processor_id();
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bc->widget_id = widget_id;
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bc->nasid = nasid;
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bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
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/*
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* point to this bridge
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*/
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bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
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/*
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* Clear all pending interrupts.
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*/
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bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
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/*
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* Until otherwise set up, assume all interrupts are from slot 0
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*/
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bridge->b_int_device = 0x0;
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/*
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* swap pio's to pci mem and io space (big windows)
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*/
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bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
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BRIDGE_CTRL_MEM_SWAP;
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#ifdef CONFIG_PAGE_SIZE_4KB
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bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
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#else /* 16kB or larger */
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bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
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#endif
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/*
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* Hmm... IRIX sets additional bits in the address which
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* are documented as reserved in the bridge docs.
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*/
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bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
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bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/
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bridge->b_dir_map = (masterwid << 20); /* DMA */
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bridge->b_int_enable = 0;
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for (slot = 0; slot < 8; slot ++) {
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bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
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bc->pci_int[slot] = -1;
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}
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bridge->b_wid_tflush; /* wait until Bridge PIO complete */
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bc->base = bridge;
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register_pci_controller(&bc->pc);
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num_bridges++;
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return 0;
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}
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/*
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* All observed requests have pin == 1. We could have a global here, that
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* gets incremented and returned every time - unfortunately, pci_map_irq
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* may be called on the same device over and over, and need to return the
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* same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
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*
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* A given PCI device, in general, should be able to intr any of the cpus
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* on any one of the hubs connected to its xbow.
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*/
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return 0;
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}
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static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
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{
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while (dev->bus->parent) {
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/* Move up the chain of bridges. */
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dev = dev->bus->self;
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}
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return dev;
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
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struct pci_dev *rdev = bridge_root_dev(dev);
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int slot = PCI_SLOT(rdev->devfn);
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int irq;
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irq = bc->pci_int[slot];
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if (irq == -1) {
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irq = request_bridge_irq(bc);
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if (irq < 0)
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return irq;
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bc->pci_int[slot] = irq;
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}
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irq_to_bridge[irq] = bc;
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irq_to_slot[irq] = slot;
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dev->irq = irq;
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return 0;
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}
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/*
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* Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
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* to find the slot number in sense of the bridge device register.
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* XXX This also means multiple devices might rely on conflicting bridge
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* settings.
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*/
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static inline void pci_disable_swapping(struct pci_dev *dev)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
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bridge_t *bridge = bc->base;
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int slot = PCI_SLOT(dev->devfn);
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/* Turn off byte swapping */
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bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
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bridge->b_widget.w_tflush; /* Flush */
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}
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static inline void pci_enable_swapping(struct pci_dev *dev)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
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bridge_t *bridge = bc->base;
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int slot = PCI_SLOT(dev->devfn);
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/* Turn on byte swapping */
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bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
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bridge->b_widget.w_tflush; /* Flush */
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}
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static void pci_fixup_ioc3(struct pci_dev *d)
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{
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pci_disable_swapping(d);
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}
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#ifdef CONFIG_NUMA
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int pcibus_to_node(struct pci_bus *bus)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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return bc->nasid;
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}
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EXPORT_SYMBOL(pcibus_to_node);
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#endif /* CONFIG_NUMA */
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
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pci_fixup_ioc3);
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