![Bartlomiej Zolnierkiewicz](/assets/img/avatar_default.png)
id->tDMA is of 'unsigned char' type so endianness is already correct and calling le16_to_cpu() is wrong. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
889 lines
21 KiB
C
889 lines
21 KiB
C
/*
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* IDE DMA support (including IDE PCI BM-DMA).
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*
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* Copyright (C) 1995-1998 Mark Lord
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* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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* DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
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*/
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/*
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* Special Thanks to Mark for his Six years of work.
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*/
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/*
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* Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
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* fixing the problem with the BIOS on some Acer motherboards.
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*
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* Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
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* "TX" chipset compatibility and for providing patches for the "TX" chipset.
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*
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* Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
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* at generic DMA -- his patches were referred to when preparing this code.
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*
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* Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
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* for supplying a Promise UDMA board & WD UDMA drive for this work!
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <linux/delay.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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static const struct drive_list_entry drive_whitelist [] = {
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{ "Micropolis 2112A" , NULL },
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{ "CONNER CTMA 4000" , NULL },
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{ "CONNER CTT8000-A" , NULL },
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{ "ST34342A" , NULL },
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{ NULL , NULL }
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};
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static const struct drive_list_entry drive_blacklist [] = {
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{ "WDC AC11000H" , NULL },
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{ "WDC AC22100H" , NULL },
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{ "WDC AC32500H" , NULL },
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{ "WDC AC33100H" , NULL },
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{ "WDC AC31600H" , NULL },
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{ "WDC AC32100H" , "24.09P07" },
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{ "WDC AC23200L" , "21.10N21" },
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{ "Compaq CRD-8241B" , NULL },
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{ "CRD-8400B" , NULL },
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{ "CRD-8480B", NULL },
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{ "CRD-8482B", NULL },
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{ "CRD-84" , NULL },
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{ "SanDisk SDP3B" , NULL },
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{ "SanDisk SDP3B-64" , NULL },
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{ "SANYO CD-ROM CRD" , NULL },
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{ "HITACHI CDR-8" , NULL },
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{ "HITACHI CDR-8335" , NULL },
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{ "HITACHI CDR-8435" , NULL },
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{ "Toshiba CD-ROM XM-6202B" , NULL },
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{ "TOSHIBA CD-ROM XM-1702BC", NULL },
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{ "CD-532E-A" , NULL },
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{ "E-IDE CD-ROM CR-840", NULL },
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{ "CD-ROM Drive/F5A", NULL },
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{ "WPI CDD-820", NULL },
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{ "SAMSUNG CD-ROM SC-148C", NULL },
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{ "SAMSUNG CD-ROM SC", NULL },
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{ "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL },
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{ "_NEC DV5800A", NULL },
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{ "SAMSUNG CD-ROM SN-124", "N001" },
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{ "Seagate STT20000A", NULL },
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{ "CD-ROM CDR_U200", "1.09" },
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{ NULL , NULL }
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};
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/**
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* ide_dma_intr - IDE DMA interrupt handler
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* @drive: the drive the interrupt is for
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*
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* Handle an interrupt completing a read/write DMA transfer on an
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* IDE device
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*/
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ide_startstop_t ide_dma_intr (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 stat = 0, dma_stat = 0;
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dma_stat = hwif->dma_ops->dma_end(drive);
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stat = hwif->tp_ops->read_status(hwif);
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if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
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if (!dma_stat) {
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struct request *rq = HWGROUP(drive)->rq;
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task_end_request(drive, rq, stat);
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return ide_stopped;
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}
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printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
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drive->name, dma_stat);
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}
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return ide_error(drive, "dma_intr", stat);
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}
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EXPORT_SYMBOL_GPL(ide_dma_intr);
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static int ide_dma_good_drive(ide_drive_t *drive)
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{
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return ide_in_drive_list(drive->id, drive_whitelist);
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}
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/**
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* ide_build_sglist - map IDE scatter gather for DMA I/O
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* @drive: the drive to build the DMA table for
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* @rq: the request holding the sg list
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*
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* Perform the DMA mapping magic necessary to access the source or
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* target buffers of a request via DMA. The lower layers of the
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* kernel provide the necessary cache management so that we can
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* operate in a portable fashion.
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*/
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int ide_build_sglist(ide_drive_t *drive, struct request *rq)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct scatterlist *sg = hwif->sg_table;
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ide_map_sg(drive, rq);
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if (rq_data_dir(rq) == READ)
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hwif->sg_dma_direction = DMA_FROM_DEVICE;
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else
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hwif->sg_dma_direction = DMA_TO_DEVICE;
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return dma_map_sg(hwif->dev, sg, hwif->sg_nents,
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hwif->sg_dma_direction);
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}
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EXPORT_SYMBOL_GPL(ide_build_sglist);
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#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
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/**
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* ide_build_dmatable - build IDE DMA table
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*
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* ide_build_dmatable() prepares a dma request. We map the command
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* to get the pci bus addresses of the buffers and then build up
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* the PRD table that the IDE layer wants to be fed. The code
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* knows about the 64K wrap bug in the CS5530.
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*
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* Returns the number of built PRD entries if all went okay,
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* returns 0 otherwise.
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*
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* May also be invoked from trm290.c
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*/
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int ide_build_dmatable (ide_drive_t *drive, struct request *rq)
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{
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ide_hwif_t *hwif = HWIF(drive);
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__le32 *table = (__le32 *)hwif->dmatable_cpu;
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unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
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unsigned int count = 0;
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int i;
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struct scatterlist *sg;
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hwif->sg_nents = i = ide_build_sglist(drive, rq);
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if (!i)
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return 0;
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sg = hwif->sg_table;
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while (i) {
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u32 cur_addr;
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u32 cur_len;
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cur_addr = sg_dma_address(sg);
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cur_len = sg_dma_len(sg);
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/*
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* Fill in the dma table, without crossing any 64kB boundaries.
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* Most hardware requires 16-bit alignment of all blocks,
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* but the trm290 requires 32-bit alignment.
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*/
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while (cur_len) {
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if (count++ >= PRD_ENTRIES) {
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printk(KERN_ERR "%s: DMA table too small\n", drive->name);
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goto use_pio_instead;
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} else {
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u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff);
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if (bcount > cur_len)
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bcount = cur_len;
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*table++ = cpu_to_le32(cur_addr);
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xcount = bcount & 0xffff;
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if (is_trm290)
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xcount = ((xcount >> 2) - 1) << 16;
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if (xcount == 0x0000) {
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/*
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* Most chipsets correctly interpret a length of 0x0000 as 64KB,
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* but at least one (e.g. CS5530) misinterprets it as zero (!).
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* So here we break the 64KB entry into two 32KB entries instead.
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*/
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if (count++ >= PRD_ENTRIES) {
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printk(KERN_ERR "%s: DMA table too small\n", drive->name);
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goto use_pio_instead;
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}
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*table++ = cpu_to_le32(0x8000);
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*table++ = cpu_to_le32(cur_addr + 0x8000);
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xcount = 0x8000;
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}
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*table++ = cpu_to_le32(xcount);
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cur_addr += bcount;
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cur_len -= bcount;
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}
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}
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sg = sg_next(sg);
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i--;
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}
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if (count) {
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if (!is_trm290)
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*--table |= cpu_to_le32(0x80000000);
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return count;
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}
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printk(KERN_ERR "%s: empty DMA table?\n", drive->name);
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use_pio_instead:
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ide_destroy_dmatable(drive);
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return 0; /* revert to PIO for this request */
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}
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EXPORT_SYMBOL_GPL(ide_build_dmatable);
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#endif
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/**
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* ide_destroy_dmatable - clean up DMA mapping
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* @drive: The drive to unmap
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*
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* Teardown mappings after DMA has completed. This must be called
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* after the completion of each use of ide_build_dmatable and before
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* the next use of ide_build_dmatable. Failure to do so will cause
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* an oops as only one mapping can be live for each target at a given
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* time.
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*/
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void ide_destroy_dmatable (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents,
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hwif->sg_dma_direction);
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}
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EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
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#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
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/**
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* config_drive_for_dma - attempt to activate IDE DMA
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* @drive: the drive to place in DMA mode
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*
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* If the drive supports at least mode 2 DMA or UDMA of any kind
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* then attempt to place it into DMA mode. Drives that are known to
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* support DMA but predate the DMA properties or that are known
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* to have DMA handling bugs are also set up appropriately based
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* on the good/bad drive lists.
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*/
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static int config_drive_for_dma (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct hd_driveid *id = drive->id;
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if (drive->media != ide_disk) {
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if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
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return 0;
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}
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/*
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* Enable DMA on any drive that has
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* UltraDMA (mode 0/1/2/3/4/5/6) enabled
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*/
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if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f))
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return 1;
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/*
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* Enable DMA on any drive that has mode2 DMA
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* (multi or single) enabled
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*/
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if (id->field_valid & 2) /* regular DMA */
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if ((id->dma_mword & 0x404) == 0x404 ||
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(id->dma_1word & 0x404) == 0x404)
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return 1;
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/* Consult the list of known "good" drives */
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if (ide_dma_good_drive(drive))
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return 1;
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return 0;
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}
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/**
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* dma_timer_expiry - handle a DMA timeout
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* @drive: Drive that timed out
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*
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* An IDE DMA transfer timed out. In the event of an error we ask
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* the driver to resolve the problem, if a DMA transfer is still
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* in progress we continue to wait (arguably we need to add a
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* secondary 'I don't care what the drive thinks' timeout here)
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* Finally if we have an interrupt we let it complete the I/O.
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* But only one time - we clear expiry and if it's still not
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* completed after WAIT_CMD, we error and retry in PIO.
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* This can occur if an interrupt is lost or due to hang or bugs.
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*/
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static int dma_timer_expiry (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
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printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n",
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drive->name, dma_stat);
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if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
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return WAIT_CMD;
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HWGROUP(drive)->expiry = NULL; /* one free ride for now */
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/* 1 dmaing, 2 error, 4 intr */
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if (dma_stat & 2) /* ERROR */
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return -1;
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if (dma_stat & 1) /* DMAing */
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return WAIT_CMD;
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if (dma_stat & 4) /* Got an Interrupt */
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return WAIT_CMD;
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return 0; /* Status is unknown -- reset the bus */
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}
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/**
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* ide_dma_host_set - Enable/disable DMA on a host
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* @drive: drive to control
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*
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* Enable/disable DMA on an IDE controller following generic
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* bus-mastering IDE controller behaviour.
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*/
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void ide_dma_host_set(ide_drive_t *drive, int on)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u8 unit = (drive->select.b.unit & 0x01);
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u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
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if (on)
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dma_stat |= (1 << (5 + unit));
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else
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dma_stat &= ~(1 << (5 + unit));
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if (hwif->host_flags & IDE_HFLAG_MMIO)
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writeb(dma_stat,
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(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
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else
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outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
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}
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EXPORT_SYMBOL_GPL(ide_dma_host_set);
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#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
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/**
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* ide_dma_off_quietly - Generic DMA kill
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* @drive: drive to control
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*
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* Turn off the current DMA on this IDE controller.
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*/
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void ide_dma_off_quietly(ide_drive_t *drive)
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{
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drive->using_dma = 0;
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ide_toggle_bounce(drive, 0);
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drive->hwif->dma_ops->dma_host_set(drive, 0);
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}
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EXPORT_SYMBOL(ide_dma_off_quietly);
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/**
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* ide_dma_off - disable DMA on a device
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* @drive: drive to disable DMA on
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*
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* Disable IDE DMA for a device on this IDE controller.
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* Inform the user that DMA has been disabled.
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*/
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void ide_dma_off(ide_drive_t *drive)
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{
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printk(KERN_INFO "%s: DMA disabled\n", drive->name);
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ide_dma_off_quietly(drive);
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}
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EXPORT_SYMBOL(ide_dma_off);
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/**
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* ide_dma_on - Enable DMA on a device
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* @drive: drive to enable DMA on
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*
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* Enable IDE DMA for a device on this IDE controller.
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*/
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void ide_dma_on(ide_drive_t *drive)
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{
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drive->using_dma = 1;
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ide_toggle_bounce(drive, 1);
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drive->hwif->dma_ops->dma_host_set(drive, 1);
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}
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#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
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/**
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* ide_dma_setup - begin a DMA phase
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* @drive: target device
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*
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* Build an IDE DMA PRD (IDE speak for scatter gather table)
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* and then set up the DMA transfer registers for a device
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* that follows generic IDE PCI DMA behaviour. Controllers can
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* override this function if they need to
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*
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* Returns 0 on success. If a PIO fallback is required then 1
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* is returned.
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*/
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int ide_dma_setup(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct request *rq = HWGROUP(drive)->rq;
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unsigned int reading;
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u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
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u8 dma_stat;
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if (rq_data_dir(rq))
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reading = 0;
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else
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reading = 1 << 3;
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/* fall back to pio! */
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if (!ide_build_dmatable(drive, rq)) {
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ide_map_sg(drive, rq);
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return 1;
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}
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/* PRD table */
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if (hwif->host_flags & IDE_HFLAG_MMIO)
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writel(hwif->dmatable_dma,
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(void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
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else
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outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
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/* specify r/w */
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if (mmio)
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writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
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else
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outb(reading, hwif->dma_base + ATA_DMA_CMD);
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/* read DMA status for INTR & ERROR flags */
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dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
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/* clear INTR & ERROR flags */
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if (mmio)
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writeb(dma_stat | 6,
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(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
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else
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outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
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drive->waiting_for_dma = 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ide_dma_setup);
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void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
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{
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/* issue cmd to drive */
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ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ide_dma_exec_cmd);
|
|
|
|
void ide_dma_start(ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = drive->hwif;
|
|
u8 dma_cmd;
|
|
|
|
/* Note that this is done *after* the cmd has
|
|
* been issued to the drive, as per the BM-IDE spec.
|
|
* The Promise Ultra33 doesn't work correctly when
|
|
* we do this part before issuing the drive cmd.
|
|
*/
|
|
if (hwif->host_flags & IDE_HFLAG_MMIO) {
|
|
dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
|
/* start DMA */
|
|
writeb(dma_cmd | 1,
|
|
(void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
|
} else {
|
|
dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
|
|
outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD);
|
|
}
|
|
|
|
hwif->dma = 1;
|
|
wmb();
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_dma_start);
|
|
|
|
/* returns 1 on error, 0 otherwise */
|
|
int __ide_dma_end (ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = drive->hwif;
|
|
u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
|
|
u8 dma_stat = 0, dma_cmd = 0;
|
|
|
|
drive->waiting_for_dma = 0;
|
|
|
|
if (mmio) {
|
|
/* get DMA command mode */
|
|
dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
|
/* stop DMA */
|
|
writeb(dma_cmd & ~1,
|
|
(void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
|
} else {
|
|
dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
|
|
outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
|
|
}
|
|
|
|
/* get DMA status */
|
|
dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
|
|
|
|
if (mmio)
|
|
/* clear the INTR & ERROR bits */
|
|
writeb(dma_stat | 6,
|
|
(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
|
|
else
|
|
outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
|
|
|
|
/* purge DMA mappings */
|
|
ide_destroy_dmatable(drive);
|
|
/* verify good DMA status */
|
|
hwif->dma = 0;
|
|
wmb();
|
|
return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_end);
|
|
|
|
/* returns 1 if dma irq issued, 0 otherwise */
|
|
int ide_dma_test_irq(ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
|
|
|
|
/* return 1 if INTR asserted */
|
|
if ((dma_stat & 4) == 4)
|
|
return 1;
|
|
if (!drive->waiting_for_dma)
|
|
printk(KERN_WARNING "%s: (%s) called while not waiting\n",
|
|
drive->name, __func__);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ide_dma_test_irq);
|
|
#else
|
|
static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; }
|
|
#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
|
|
|
|
int __ide_dma_bad_drive (ide_drive_t *drive)
|
|
{
|
|
struct hd_driveid *id = drive->id;
|
|
|
|
int blacklist = ide_in_drive_list(id, drive_blacklist);
|
|
if (blacklist) {
|
|
printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
|
|
drive->name, id->model);
|
|
return blacklist;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_bad_drive);
|
|
|
|
static const u8 xfer_mode_bases[] = {
|
|
XFER_UDMA_0,
|
|
XFER_MW_DMA_0,
|
|
XFER_SW_DMA_0,
|
|
};
|
|
|
|
static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode)
|
|
{
|
|
struct hd_driveid *id = drive->id;
|
|
ide_hwif_t *hwif = drive->hwif;
|
|
const struct ide_port_ops *port_ops = hwif->port_ops;
|
|
unsigned int mask = 0;
|
|
|
|
switch(base) {
|
|
case XFER_UDMA_0:
|
|
if ((id->field_valid & 4) == 0)
|
|
break;
|
|
|
|
if (port_ops && port_ops->udma_filter)
|
|
mask = port_ops->udma_filter(drive);
|
|
else
|
|
mask = hwif->ultra_mask;
|
|
mask &= id->dma_ultra;
|
|
|
|
/*
|
|
* avoid false cable warning from eighty_ninty_three()
|
|
*/
|
|
if (req_mode > XFER_UDMA_2) {
|
|
if ((mask & 0x78) && (eighty_ninty_three(drive) == 0))
|
|
mask &= 0x07;
|
|
}
|
|
break;
|
|
case XFER_MW_DMA_0:
|
|
if ((id->field_valid & 2) == 0)
|
|
break;
|
|
if (port_ops && port_ops->mdma_filter)
|
|
mask = port_ops->mdma_filter(drive);
|
|
else
|
|
mask = hwif->mwdma_mask;
|
|
mask &= id->dma_mword;
|
|
break;
|
|
case XFER_SW_DMA_0:
|
|
if (id->field_valid & 2) {
|
|
mask = id->dma_1word & hwif->swdma_mask;
|
|
} else if (id->tDMA) {
|
|
u8 mode = id->tDMA;
|
|
|
|
/*
|
|
* if the mode is valid convert it to the mask
|
|
* (the maximum allowed mode is XFER_SW_DMA_2)
|
|
*/
|
|
if (mode <= 2)
|
|
mask = ((2 << mode) - 1) & hwif->swdma_mask;
|
|
}
|
|
break;
|
|
default:
|
|
BUG();
|
|
break;
|
|
}
|
|
|
|
return mask;
|
|
}
|
|
|
|
/**
|
|
* ide_find_dma_mode - compute DMA speed
|
|
* @drive: IDE device
|
|
* @req_mode: requested mode
|
|
*
|
|
* Checks the drive/host capabilities and finds the speed to use for
|
|
* the DMA transfer. The speed is then limited by the requested mode.
|
|
*
|
|
* Returns 0 if the drive/host combination is incapable of DMA transfers
|
|
* or if the requested mode is not a DMA mode.
|
|
*/
|
|
|
|
u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode)
|
|
{
|
|
ide_hwif_t *hwif = drive->hwif;
|
|
unsigned int mask;
|
|
int x, i;
|
|
u8 mode = 0;
|
|
|
|
if (drive->media != ide_disk) {
|
|
if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) {
|
|
if (req_mode < xfer_mode_bases[i])
|
|
continue;
|
|
mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode);
|
|
x = fls(mask) - 1;
|
|
if (x >= 0) {
|
|
mode = xfer_mode_bases[i] + x;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (hwif->chipset == ide_acorn && mode == 0) {
|
|
/*
|
|
* is this correct?
|
|
*/
|
|
if (ide_dma_good_drive(drive) && drive->id->eide_dma_time < 150)
|
|
mode = XFER_MW_DMA_1;
|
|
}
|
|
|
|
mode = min(mode, req_mode);
|
|
|
|
printk(KERN_INFO "%s: %s mode selected\n", drive->name,
|
|
mode ? ide_xfer_verbose(mode) : "no DMA");
|
|
|
|
return mode;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_find_dma_mode);
|
|
|
|
static int ide_tune_dma(ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = drive->hwif;
|
|
u8 speed;
|
|
|
|
if (drive->nodma || (drive->id->capability & 1) == 0)
|
|
return 0;
|
|
|
|
/* consult the list of known "bad" drives */
|
|
if (__ide_dma_bad_drive(drive))
|
|
return 0;
|
|
|
|
if (ide_id_dma_bug(drive))
|
|
return 0;
|
|
|
|
if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA)
|
|
return config_drive_for_dma(drive);
|
|
|
|
speed = ide_max_dma_mode(drive);
|
|
|
|
if (!speed)
|
|
return 0;
|
|
|
|
if (ide_set_dma_mode(drive, speed))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int ide_dma_check(ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = drive->hwif;
|
|
|
|
if (ide_tune_dma(drive))
|
|
return 0;
|
|
|
|
/* TODO: always do PIO fallback */
|
|
if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA)
|
|
return -1;
|
|
|
|
ide_set_max_pio(drive);
|
|
|
|
return -1;
|
|
}
|
|
|
|
int ide_id_dma_bug(ide_drive_t *drive)
|
|
{
|
|
struct hd_driveid *id = drive->id;
|
|
|
|
if (id->field_valid & 4) {
|
|
if ((id->dma_ultra >> 8) && (id->dma_mword >> 8))
|
|
goto err_out;
|
|
} else if (id->field_valid & 2) {
|
|
if ((id->dma_mword >> 8) && (id->dma_1word >> 8))
|
|
goto err_out;
|
|
}
|
|
return 0;
|
|
err_out:
|
|
printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name);
|
|
return 1;
|
|
}
|
|
|
|
int ide_set_dma(ide_drive_t *drive)
|
|
{
|
|
int rc;
|
|
|
|
/*
|
|
* Force DMAing for the beginning of the check.
|
|
* Some chipsets appear to do interesting
|
|
* things, if not checked and cleared.
|
|
* PARANOIA!!!
|
|
*/
|
|
ide_dma_off_quietly(drive);
|
|
|
|
rc = ide_dma_check(drive);
|
|
if (rc)
|
|
return rc;
|
|
|
|
ide_dma_on(drive);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ide_check_dma_crc(ide_drive_t *drive)
|
|
{
|
|
u8 mode;
|
|
|
|
ide_dma_off_quietly(drive);
|
|
drive->crc_count = 0;
|
|
mode = drive->current_speed;
|
|
/*
|
|
* Don't try non Ultra-DMA modes without iCRC's. Force the
|
|
* device to PIO and make the user enable SWDMA/MWDMA modes.
|
|
*/
|
|
if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7)
|
|
mode--;
|
|
else
|
|
mode = XFER_PIO_4;
|
|
ide_set_xfer_rate(drive, mode);
|
|
if (drive->current_speed >= XFER_SW_DMA_0)
|
|
ide_dma_on(drive);
|
|
}
|
|
|
|
#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
|
|
void ide_dma_lost_irq (ide_drive_t *drive)
|
|
{
|
|
printk("%s: DMA interrupt recovery\n", drive->name);
|
|
}
|
|
|
|
EXPORT_SYMBOL(ide_dma_lost_irq);
|
|
|
|
void ide_dma_timeout (ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
|
|
printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
|
|
|
|
if (hwif->dma_ops->dma_test_irq(drive))
|
|
return;
|
|
|
|
hwif->dma_ops->dma_end(drive);
|
|
}
|
|
|
|
EXPORT_SYMBOL(ide_dma_timeout);
|
|
|
|
void ide_release_dma_engine(ide_hwif_t *hwif)
|
|
{
|
|
if (hwif->dmatable_cpu) {
|
|
struct pci_dev *pdev = to_pci_dev(hwif->dev);
|
|
|
|
pci_free_consistent(pdev, PRD_ENTRIES * PRD_BYTES,
|
|
hwif->dmatable_cpu, hwif->dmatable_dma);
|
|
hwif->dmatable_cpu = NULL;
|
|
}
|
|
}
|
|
|
|
int ide_allocate_dma_engine(ide_hwif_t *hwif)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(hwif->dev);
|
|
|
|
hwif->dmatable_cpu = pci_alloc_consistent(pdev,
|
|
PRD_ENTRIES * PRD_BYTES,
|
|
&hwif->dmatable_dma);
|
|
|
|
if (hwif->dmatable_cpu)
|
|
return 0;
|
|
|
|
printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n",
|
|
hwif->name);
|
|
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ide_allocate_dma_engine);
|
|
|
|
const struct ide_dma_ops sff_dma_ops = {
|
|
.dma_host_set = ide_dma_host_set,
|
|
.dma_setup = ide_dma_setup,
|
|
.dma_exec_cmd = ide_dma_exec_cmd,
|
|
.dma_start = ide_dma_start,
|
|
.dma_end = __ide_dma_end,
|
|
.dma_test_irq = ide_dma_test_irq,
|
|
.dma_timeout = ide_dma_timeout,
|
|
.dma_lost_irq = ide_dma_lost_irq,
|
|
};
|
|
EXPORT_SYMBOL_GPL(sff_dma_ops);
|
|
#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
|