Mark Zhang 7c4b1ab9f1 IB/mlx5: Add DCT RoCE LAG support ... When DCT QPs work in RoCE LAG mode: 1. DCT creation is allowed only when it is supported 2. The "port" of a DCT QP is assigned in a round-robin way Link: https://lore.kernel.org/r/20200818115245.700581-3-leon@kernel.org Signed-off-by: Mark Zhang <markz@mellanox.com> Reviewed-by: Maor Gottlieb <maorg@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>		2020-08-27 08:34:28 -03:00
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accel.h	net/mlx5: Accel, Add core IPsec support for the Connect-X family	2020-07-16 16:36:42 -07:00
cq.h	net/mlx5: Avoid RDMA file inclusion in core driver	2020-06-27 13:50:46 -07:00
device.h	RDMA/mlx5: Set mkey relaxed ordering by UMR with ConnectX-7	2020-07-27 11:19:00 -03:00
doorbell.h
driver.h	RDMA 5.9 merge window pull request	2020-08-06 16:43:36 -07:00
eq.h
eswitch.h
fs.h	net/mlx5: Add IPsec related Flow steering entry's fields	2020-07-16 16:36:46 -07:00
fs_helpers.h
mlx5_ifc.h	IB/mlx5: Add DCT RoCE LAG support	2020-08-27 08:34:28 -03:00
mlx5_ifc_fpga.h
port.h	net/mlx5: Added support for 100Gbps per lane link modes	2020-07-08 15:30:42 -07:00
qp.h	net/mlx5: kTLS, Improve TLS params layout structures	2020-06-27 13:50:46 -07:00
rsc_dump.h	net/mlx5: Add support in query QP, CQ and MKEY segments	2020-06-23 17:26:10 +03:00
transobj.h
vport.h	net/mlx5: Constify mac address pointer	2020-06-22 15:29:19 -07:00