![Russell King](/assets/img/avatar_default.png)
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
540 lines
13 KiB
C
540 lines
13 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.c
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2008 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/cpufreq.h>
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#include <mach/clock.h>
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#include <mach/sram.h>
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#include <asm/div64.h>
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#include <asm/bitops.h>
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#include "memory.h"
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#include "clock.h"
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#include "clock24xx.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
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#define EN_APLL_STOPPED 0
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#define EN_APLL_LOCKED 3
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/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
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#define APLLS_CLKIN_19_2MHZ 0
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#define APLLS_CLKIN_13MHZ 2
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#define APLLS_CLKIN_12MHZ 3
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/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
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static struct prcm_config *curr_prcm_set;
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static struct clk *vclk;
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static struct clk *sclk;
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/*-------------------------------------------------------------------------
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* Omap24xx specific clock functions
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*-------------------------------------------------------------------------*/
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/* This actually returns the rate of core_ck, not dpll_ck. */
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static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
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{
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long long dpll_clk;
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u8 amult;
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dpll_clk = omap2_get_dpll_rate(tclk);
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amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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amult &= OMAP24XX_CORE_CLK_SRC_MASK;
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dpll_clk *= amult;
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return dpll_clk;
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}
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static int omap2_enable_osc_ck(struct clk *clk)
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{
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u32 pcc;
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pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
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__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
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OMAP24XX_PRCM_CLKSRC_CTRL);
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return 0;
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}
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static void omap2_disable_osc_ck(struct clk *clk)
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{
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u32 pcc;
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pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
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__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
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OMAP24XX_PRCM_CLKSRC_CTRL);
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}
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#ifdef OLD_CK
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/* Recalculate SYST_CLK */
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static void omap2_sys_clk_recalc(struct clk * clk)
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{
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u32 div = PRCM_CLKSRC_CTRL;
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div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
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div >>= clk->rate_offset;
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clk->rate = (clk->parent->rate / div);
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propagate_rate(clk);
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}
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#endif /* OLD_CK */
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/* Enable an APLL if off */
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static int omap2_clk_fixed_enable(struct clk *clk)
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{
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u32 cval, apll_mask;
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apll_mask = EN_APLL_LOCKED << clk->enable_bit;
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cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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if ((cval & apll_mask) == apll_mask)
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return 0; /* apll already enabled */
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cval &= ~apll_mask;
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cval |= apll_mask;
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cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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if (clk == &apll96_ck)
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cval = OMAP24XX_ST_96M_APLL;
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else if (clk == &apll54_ck)
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cval = OMAP24XX_ST_54M_APLL;
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omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
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clk->name);
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/*
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* REVISIT: Should we return an error code if omap2_wait_clock_ready()
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* fails?
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*/
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return 0;
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}
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/* Stop APLL */
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static void omap2_clk_fixed_disable(struct clk *clk)
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{
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u32 cval;
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cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
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cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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}
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/*
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* Uses the current prcm set to tell if a rate is valid.
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* You can go slower, but not faster within a given rate set.
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*/
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long omap2_dpllcore_round_rate(unsigned long target_rate)
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{
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u32 high, low, core_clk_src;
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core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
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if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
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high = curr_prcm_set->dpll_speed * 2;
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low = curr_prcm_set->dpll_speed;
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} else { /* DPLL clockout x 2 */
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high = curr_prcm_set->dpll_speed;
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low = curr_prcm_set->dpll_speed / 2;
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}
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#ifdef DOWN_VARIABLE_DPLL
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if (target_rate > high)
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return high;
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else
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return target_rate;
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#else
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if (target_rate > low)
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return high;
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else
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return low;
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#endif
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}
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static void omap2_dpllcore_recalc(struct clk *clk)
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{
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clk->rate = omap2_get_dpll_rate_24xx(clk);
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propagate_rate(clk);
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}
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static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
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{
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u32 cur_rate, low, mult, div, valid_rate, done_rate;
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u32 bypass = 0;
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struct prcm_config tmpset;
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const struct dpll_data *dd;
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unsigned long flags;
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int ret = -EINVAL;
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local_irq_save(flags);
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cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
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mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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mult &= OMAP24XX_CORE_CLK_SRC_MASK;
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if ((rate == (cur_rate / 2)) && (mult == 2)) {
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omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
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} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
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omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
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} else if (rate != cur_rate) {
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valid_rate = omap2_dpllcore_round_rate(rate);
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if (valid_rate != rate)
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goto dpll_exit;
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if (mult == 1)
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low = curr_prcm_set->dpll_speed;
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else
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low = curr_prcm_set->dpll_speed / 2;
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dd = clk->dpll_data;
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if (!dd)
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goto dpll_exit;
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tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
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tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
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dd->div1_mask);
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div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
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tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
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if (rate > low) {
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tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
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mult = ((rate / 2) / 1000000);
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done_rate = CORE_CLK_SRC_DPLL_X2;
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} else {
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tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
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mult = (rate / 1000000);
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done_rate = CORE_CLK_SRC_DPLL;
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}
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tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
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tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
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/* Worst case */
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tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
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if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
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bypass = 1;
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omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
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/* Force dll lock mode */
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omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
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bypass);
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/* Errata: ret dll entry state */
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omap2_init_memory_params(omap2_dll_force_needed());
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omap2_reprogram_sdrc(done_rate, 0);
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}
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omap2_dpllcore_recalc(&dpll_ck);
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ret = 0;
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dpll_exit:
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local_irq_restore(flags);
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return(ret);
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}
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/**
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* omap2_table_mpu_recalc - just return the MPU speed
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* @clk: virt_prcm_set struct clk
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*
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* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
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*/
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static void omap2_table_mpu_recalc(struct clk *clk)
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{
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clk->rate = curr_prcm_set->mpu_speed;
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}
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/*
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* Look for a rate equal or less than the target rate given a configuration set.
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*
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* What's not entirely clear is "which" field represents the key field.
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* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
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* just uses the ARM rates.
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*/
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static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
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{
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struct prcm_config *ptr;
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long highest_rate;
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if (clk != &virt_prcm_set)
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return -EINVAL;
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highest_rate = -EINVAL;
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for (ptr = rate_table; ptr->mpu_speed; ptr++) {
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if (!(ptr->flags & cpu_mask))
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continue;
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if (ptr->xtal_speed != sys_ck.rate)
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continue;
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highest_rate = ptr->mpu_speed;
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/* Can check only after xtal frequency check */
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if (ptr->mpu_speed <= rate)
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break;
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}
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return highest_rate;
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}
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/* Sets basic clocks based on the specified rate */
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static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
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{
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u32 cur_rate, done_rate, bypass = 0, tmp;
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struct prcm_config *prcm;
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unsigned long found_speed = 0;
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unsigned long flags;
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if (clk != &virt_prcm_set)
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return -EINVAL;
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for (prcm = rate_table; prcm->mpu_speed; prcm++) {
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if (!(prcm->flags & cpu_mask))
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continue;
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if (prcm->xtal_speed != sys_ck.rate)
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continue;
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if (prcm->mpu_speed <= rate) {
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found_speed = prcm->mpu_speed;
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break;
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}
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}
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if (!found_speed) {
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printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
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rate / 1000000);
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return -EINVAL;
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}
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curr_prcm_set = prcm;
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cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
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if (prcm->dpll_speed == cur_rate / 2) {
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omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
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} else if (prcm->dpll_speed == cur_rate * 2) {
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omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
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} else if (prcm->dpll_speed != cur_rate) {
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local_irq_save(flags);
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if (prcm->dpll_speed == prcm->xtal_speed)
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bypass = 1;
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if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
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CORE_CLK_SRC_DPLL_X2)
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done_rate = CORE_CLK_SRC_DPLL_X2;
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else
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done_rate = CORE_CLK_SRC_DPLL;
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/* MPU divider */
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cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
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/* dsp + iva1 div(2420), iva2.1(2430) */
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cm_write_mod_reg(prcm->cm_clksel_dsp,
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OMAP24XX_DSP_MOD, CM_CLKSEL);
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cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
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/* Major subsystem dividers */
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tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
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cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
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if (cpu_is_omap2430())
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cm_write_mod_reg(prcm->cm_clksel_mdm,
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OMAP2430_MDM_MOD, CM_CLKSEL);
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/* x2 to enter init_mem */
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omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
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omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
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bypass);
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omap2_init_memory_params(omap2_dll_force_needed());
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omap2_reprogram_sdrc(done_rate, 0);
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local_irq_restore(flags);
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}
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omap2_dpllcore_recalc(&dpll_ck);
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return 0;
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}
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static struct clk_functions omap2_clk_functions = {
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.clk_enable = omap2_clk_enable,
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.clk_disable = omap2_clk_disable,
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.clk_round_rate = omap2_clk_round_rate,
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.clk_set_rate = omap2_clk_set_rate,
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.clk_set_parent = omap2_clk_set_parent,
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.clk_disable_unused = omap2_clk_disable_unused,
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};
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static u32 omap2_get_apll_clkin(void)
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{
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u32 aplls, sclk = 0;
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aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
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aplls &= OMAP24XX_APLLS_CLKIN_MASK;
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aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
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if (aplls == APLLS_CLKIN_19_2MHZ)
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sclk = 19200000;
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else if (aplls == APLLS_CLKIN_13MHZ)
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sclk = 13000000;
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else if (aplls == APLLS_CLKIN_12MHZ)
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sclk = 12000000;
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return sclk;
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}
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static u32 omap2_get_sysclkdiv(void)
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{
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u32 div;
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div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
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div &= OMAP_SYSCLKDIV_MASK;
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div >>= OMAP_SYSCLKDIV_SHIFT;
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return div;
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}
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static void omap2_osc_clk_recalc(struct clk *clk)
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{
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clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
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propagate_rate(clk);
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}
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static void omap2_sys_clk_recalc(struct clk *clk)
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{
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clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
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propagate_rate(clk);
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}
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/*
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* Set clocks for bypass mode for reboot to work.
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*/
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void omap2_clk_prepare_for_reboot(void)
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{
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u32 rate;
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if (vclk == NULL || sclk == NULL)
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return;
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rate = clk_get_rate(sclk);
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clk_set_rate(vclk, rate);
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}
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/*
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* Switch the MPU rate if specified on cmdline.
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* We cannot do this early until cmdline is parsed.
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*/
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static int __init omap2_clk_arch_init(void)
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{
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if (!mpurate)
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return -EINVAL;
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if (omap2_select_table_rate(&virt_prcm_set, mpurate))
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printk(KERN_ERR "Could not find matching MPU rate\n");
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recalculate_root_clocks();
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printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
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(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
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return 0;
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}
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arch_initcall(omap2_clk_arch_init);
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int __init omap2_clk_init(void)
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{
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struct prcm_config *prcm;
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struct clk **clkp;
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u32 clkrate;
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if (cpu_is_omap242x())
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cpu_mask = RATE_IN_242X;
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else if (cpu_is_omap2430())
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cpu_mask = RATE_IN_243X;
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clk_init(&omap2_clk_functions);
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omap2_osc_clk_recalc(&osc_ck);
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omap2_sys_clk_recalc(&sys_ck);
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for (clkp = onchip_24xx_clks;
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clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
|
|
clkp++) {
|
|
|
|
if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
|
|
if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
|
|
clk_register(*clkp);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
/* Check the MPU rate set by bootloader */
|
|
clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
|
|
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
|
if (!(prcm->flags & cpu_mask))
|
|
continue;
|
|
if (prcm->xtal_speed != sys_ck.rate)
|
|
continue;
|
|
if (prcm->dpll_speed <= clkrate)
|
|
break;
|
|
}
|
|
curr_prcm_set = prcm;
|
|
|
|
recalculate_root_clocks();
|
|
|
|
printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
|
|
"%ld.%01ld/%ld/%ld MHz\n",
|
|
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
|
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
|
|
|
/*
|
|
* Only enable those clocks we will need, let the drivers
|
|
* enable other clocks as necessary
|
|
*/
|
|
clk_enable_init_clocks();
|
|
|
|
/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
|
|
vclk = clk_get(NULL, "virt_prcm_set");
|
|
sclk = clk_get(NULL, "sys_ck");
|
|
|
|
return 0;
|
|
}
|