e8a91c953f
OMAP1_IO_ADDRESS(), OMAP2_IO_ADDRESS() and IO_ADDRESS() returns cookies
for use with __raw_{read|write}* for accessing registers. Therefore,
these macros should return (void __iomem *) cookies, not integer values.
Doing this improves typechecking, and means we can find those places
where, eg, DMA controllers are incorrectly given virtual addresses to
DMA to, or physical addresses are thrown through a virtual to physical
address translation.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
141 lines
3.2 KiB
C
141 lines
3.2 KiB
C
/*
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* linux/arch/arm/mach-omap2/irq.c
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*
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* Interrupt handler for OMAP2 boards.
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <mach/hardware.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#define INTC_REVISION 0x0000
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#define INTC_SYSCONFIG 0x0010
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#define INTC_SYSSTATUS 0x0014
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#define INTC_CONTROL 0x0048
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#define INTC_MIR_CLEAR0 0x0088
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#define INTC_MIR_SET0 0x008c
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/*
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* OMAP2 has a number of different interrupt controllers, each interrupt
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* controller is identified as its own "bank". Register definitions are
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* fairly consistent for each bank, but not all registers are implemented
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* for each bank.. when in doubt, consult the TRM.
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*/
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static struct omap_irq_bank {
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void __iomem *base_reg;
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unsigned int nr_irqs;
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} __attribute__ ((aligned(4))) irq_banks[] = {
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{
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/* MPU INTC */
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.base_reg = IO_ADDRESS(OMAP24XX_IC_BASE),
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.nr_irqs = 96,
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}, {
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/* XXX: DSP INTC */
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}
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};
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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static void omap_ack_irq(unsigned int irq)
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{
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__raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
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}
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static void omap_mask_irq(unsigned int irq)
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{
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int offset = (irq >> 5) << 5;
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if (irq >= 64) {
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irq %= 64;
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} else if (irq >= 32) {
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irq %= 32;
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}
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__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
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}
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static void omap_unmask_irq(unsigned int irq)
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{
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int offset = (irq >> 5) << 5;
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if (irq >= 64) {
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irq %= 64;
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} else if (irq >= 32) {
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irq %= 32;
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}
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__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
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}
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static void omap_mask_ack_irq(unsigned int irq)
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{
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omap_mask_irq(irq);
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omap_ack_irq(irq);
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}
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static struct irq_chip omap_irq_chip = {
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.name = "INTC",
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.ack = omap_mask_ack_irq,
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.mask = omap_mask_irq,
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.unmask = omap_unmask_irq,
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};
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static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
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{
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unsigned long tmp;
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tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
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printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
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"(revision %ld.%ld) with %d interrupts\n",
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bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
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tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
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tmp |= 1 << 1; /* soft reset */
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__raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
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while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
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/* Wait for reset to complete */;
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/* Enable autoidle */
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__raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
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}
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void __init omap_init_irq(void)
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{
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unsigned long nr_irqs = 0;
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unsigned int nr_banks = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
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struct omap_irq_bank *bank = irq_banks + i;
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/* XXX */
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if (!bank->base_reg)
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continue;
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omap_irq_bank_init_one(bank);
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nr_irqs += bank->nr_irqs;
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nr_banks++;
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}
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printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
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nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
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for (i = 0; i < nr_irqs; i++) {
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set_irq_chip(i, &omap_irq_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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}
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