55b8fd4f42
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
37 lines
838 B
C
37 lines
838 B
C
/*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* SPEAr clk - Common routines
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*/
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#include <linux/clk-provider.h>
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#include <linux/types.h>
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#include "clk.h"
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long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
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unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
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int *index)
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{
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unsigned long prev_rate, rate = 0;
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for (*index = 0; *index < rtbl_cnt; (*index)++) {
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prev_rate = rate;
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rate = calc_rate(hw, parent_rate, *index);
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if (drate < rate) {
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/* previous clock was best */
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if (*index) {
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rate = prev_rate;
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(*index)--;
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}
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break;
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}
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}
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return rate;
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}
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