![Angelo Dureghello](/assets/img/avatar_default.png)
Due to recent fixes in m68k arch-specific I/O accessor macros, this driver is not working anymore for ColdFire. Fix wrong tcd endianness removing additional swaps, since edma_writex() functions should already take care of any eventual swap if needed. Note, i could only test the change in ColdFire mcf54415 and Vybrid vf50 / Colibri where i don't see any issue. So, every feedback and test for all other SoCs involved is really appreciated. Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> Reported-by: kbuild test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20200701225205.1674463-1-angelo.dureghello@timesys.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
719 lines
20 KiB
C
719 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
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// Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it>
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#include <linux/dmapool.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include "fsl-edma-common.h"
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#define EDMA_CR 0x00
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#define EDMA_ES 0x04
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#define EDMA_ERQ 0x0C
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#define EDMA_EEI 0x14
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#define EDMA_SERQ 0x1B
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#define EDMA_CERQ 0x1A
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#define EDMA_SEEI 0x19
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#define EDMA_CEEI 0x18
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#define EDMA_CINT 0x1F
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#define EDMA_CERR 0x1E
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#define EDMA_SSRT 0x1D
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#define EDMA_CDNE 0x1C
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#define EDMA_INTR 0x24
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#define EDMA_ERR 0x2C
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#define EDMA64_ERQH 0x08
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#define EDMA64_EEIH 0x10
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#define EDMA64_SERQ 0x18
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#define EDMA64_CERQ 0x19
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#define EDMA64_SEEI 0x1a
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#define EDMA64_CEEI 0x1b
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#define EDMA64_CINT 0x1c
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#define EDMA64_CERR 0x1d
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#define EDMA64_SSRT 0x1e
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#define EDMA64_CDNE 0x1f
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#define EDMA64_INTH 0x20
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#define EDMA64_INTL 0x24
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#define EDMA64_ERRH 0x28
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#define EDMA64_ERRL 0x2c
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#define EDMA_TCD 0x1000
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static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
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{
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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if (fsl_chan->edma->drvdata->version == v1) {
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edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
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edma_writeb(fsl_chan->edma, ch, regs->serq);
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} else {
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/* ColdFire is big endian, and accesses natively
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* big endian I/O peripherals
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*/
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iowrite8(EDMA_SEEI_SEEI(ch), regs->seei);
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iowrite8(ch, regs->serq);
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}
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}
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void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
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{
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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if (fsl_chan->edma->drvdata->version == v1) {
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edma_writeb(fsl_chan->edma, ch, regs->cerq);
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edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
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} else {
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/* ColdFire is big endian, and accesses natively
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* big endian I/O peripherals
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*/
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iowrite8(ch, regs->cerq);
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iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
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}
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}
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EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
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static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
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u32 off, u32 slot, bool enable)
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{
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u8 val8;
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if (enable)
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val8 = EDMAMUX_CHCFG_ENBL | slot;
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else
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val8 = EDMAMUX_CHCFG_DIS;
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iowrite8(val8, addr + off);
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}
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static void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
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u32 off, u32 slot, bool enable)
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{
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u32 val;
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if (enable)
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val = EDMAMUX_CHCFG_ENBL << 24 | slot;
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else
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val = EDMAMUX_CHCFG_DIS;
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iowrite32(val, addr + off * 4);
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}
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void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
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unsigned int slot, bool enable)
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{
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u32 ch = fsl_chan->vchan.chan.chan_id;
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void __iomem *muxaddr;
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unsigned int chans_per_mux, ch_off;
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int endian_diff[4] = {3, 1, -1, -3};
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u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs;
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chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr;
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ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
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if (fsl_chan->edma->drvdata->mux_swap)
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ch_off += endian_diff[ch_off % 4];
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muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
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slot = EDMAMUX_CHCFG_SOURCE(slot);
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if (fsl_chan->edma->drvdata->version == v3)
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mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable);
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else
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mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
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}
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EXPORT_SYMBOL_GPL(fsl_edma_chan_mux);
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static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
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{
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switch (addr_width) {
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case 1:
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return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT;
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case 2:
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return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT;
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case 4:
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return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
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case 8:
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return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT;
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default:
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return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
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}
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}
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void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
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{
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struct fsl_edma_desc *fsl_desc;
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int i;
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fsl_desc = to_fsl_edma_desc(vdesc);
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for (i = 0; i < fsl_desc->n_tcds; i++)
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dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd,
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fsl_desc->tcd[i].ptcd);
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kfree(fsl_desc);
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}
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EXPORT_SYMBOL_GPL(fsl_edma_free_desc);
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int fsl_edma_terminate_all(struct dma_chan *chan)
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{
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struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
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fsl_edma_disable_request(fsl_chan);
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fsl_chan->edesc = NULL;
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fsl_chan->idle = true;
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vchan_get_all_descriptors(&fsl_chan->vchan, &head);
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spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
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vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
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return 0;
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}
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EXPORT_SYMBOL_GPL(fsl_edma_terminate_all);
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int fsl_edma_pause(struct dma_chan *chan)
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{
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struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
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if (fsl_chan->edesc) {
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fsl_edma_disable_request(fsl_chan);
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fsl_chan->status = DMA_PAUSED;
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fsl_chan->idle = true;
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}
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spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(fsl_edma_pause);
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int fsl_edma_resume(struct dma_chan *chan)
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{
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struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
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if (fsl_chan->edesc) {
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fsl_edma_enable_request(fsl_chan);
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fsl_chan->status = DMA_IN_PROGRESS;
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fsl_chan->idle = false;
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}
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spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(fsl_edma_resume);
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static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan)
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{
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if (fsl_chan->dma_dir != DMA_NONE)
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dma_unmap_resource(fsl_chan->vchan.chan.device->dev,
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fsl_chan->dma_dev_addr,
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fsl_chan->dma_dev_size,
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fsl_chan->dma_dir, 0);
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fsl_chan->dma_dir = DMA_NONE;
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}
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static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan,
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enum dma_transfer_direction dir)
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{
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struct device *dev = fsl_chan->vchan.chan.device->dev;
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enum dma_data_direction dma_dir;
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phys_addr_t addr = 0;
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u32 size = 0;
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switch (dir) {
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case DMA_MEM_TO_DEV:
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dma_dir = DMA_FROM_DEVICE;
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addr = fsl_chan->cfg.dst_addr;
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size = fsl_chan->cfg.dst_maxburst;
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break;
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case DMA_DEV_TO_MEM:
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dma_dir = DMA_TO_DEVICE;
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addr = fsl_chan->cfg.src_addr;
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size = fsl_chan->cfg.src_maxburst;
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break;
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default:
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dma_dir = DMA_NONE;
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break;
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}
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/* Already mapped for this config? */
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if (fsl_chan->dma_dir == dma_dir)
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return true;
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fsl_edma_unprep_slave_dma(fsl_chan);
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fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0);
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if (dma_mapping_error(dev, fsl_chan->dma_dev_addr))
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return false;
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fsl_chan->dma_dev_size = size;
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fsl_chan->dma_dir = dma_dir;
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return true;
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}
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int fsl_edma_slave_config(struct dma_chan *chan,
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struct dma_slave_config *cfg)
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{
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struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
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memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg));
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fsl_edma_unprep_slave_dma(fsl_chan);
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return 0;
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}
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EXPORT_SYMBOL_GPL(fsl_edma_slave_config);
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static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
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struct virt_dma_desc *vdesc, bool in_progress)
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{
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struct fsl_edma_desc *edesc = fsl_chan->edesc;
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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enum dma_transfer_direction dir = edesc->dirn;
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dma_addr_t cur_addr, dma_addr;
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size_t len, size;
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int i;
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/* calculate the total size in this desc */
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for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
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len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
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* le16_to_cpu(edesc->tcd[i].vtcd->biter);
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if (!in_progress)
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return len;
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if (dir == DMA_MEM_TO_DEV)
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cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr);
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else
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cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr);
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/* figure out the finished and calculate the residue */
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for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
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size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
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* le16_to_cpu(edesc->tcd[i].vtcd->biter);
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if (dir == DMA_MEM_TO_DEV)
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dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr);
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else
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dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr);
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len -= size;
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if (cur_addr >= dma_addr && cur_addr < dma_addr + size) {
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len += dma_addr + size - cur_addr;
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break;
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}
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}
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return len;
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}
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enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *txstate)
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{
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struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
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struct virt_dma_desc *vdesc;
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enum dma_status status;
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unsigned long flags;
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status = dma_cookie_status(chan, cookie, txstate);
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if (status == DMA_COMPLETE)
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return status;
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if (!txstate)
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return fsl_chan->status;
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spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
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vdesc = vchan_find_desc(&fsl_chan->vchan, cookie);
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if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie)
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txstate->residue =
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fsl_edma_desc_residue(fsl_chan, vdesc, true);
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else if (vdesc)
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txstate->residue =
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fsl_edma_desc_residue(fsl_chan, vdesc, false);
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else
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txstate->residue = 0;
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spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
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return fsl_chan->status;
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}
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EXPORT_SYMBOL_GPL(fsl_edma_tx_status);
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static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
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struct fsl_edma_hw_tcd *tcd)
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{
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struct fsl_edma_engine *edma = fsl_chan->edma;
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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/*
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* TCD parameters are stored in struct fsl_edma_hw_tcd in little
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* endian format. However, we need to load the TCD registers in
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* big- or little-endian obeying the eDMA engine model endian,
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* and this is performed from specific edma_write functions
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*/
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edma_writew(edma, 0, ®s->tcd[ch].csr);
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edma_writel(edma, (s32)tcd->saddr, ®s->tcd[ch].saddr);
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edma_writel(edma, (s32)tcd->daddr, ®s->tcd[ch].daddr);
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edma_writew(edma, (s16)tcd->attr, ®s->tcd[ch].attr);
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edma_writew(edma, tcd->soff, ®s->tcd[ch].soff);
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edma_writel(edma, (s32)tcd->nbytes, ®s->tcd[ch].nbytes);
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edma_writel(edma, (s32)tcd->slast, ®s->tcd[ch].slast);
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edma_writew(edma, (s16)tcd->citer, ®s->tcd[ch].citer);
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edma_writew(edma, (s16)tcd->biter, ®s->tcd[ch].biter);
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edma_writew(edma, (s16)tcd->doff, ®s->tcd[ch].doff);
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edma_writel(edma, (s32)tcd->dlast_sga,
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®s->tcd[ch].dlast_sga);
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edma_writew(edma, (s16)tcd->csr, ®s->tcd[ch].csr);
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}
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static inline
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void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
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u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
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u16 biter, u16 doff, u32 dlast_sga, bool major_int,
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bool disable_req, bool enable_sg)
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{
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u16 csr = 0;
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/*
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* eDMA hardware SGs require the TCDs to be stored in little
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* endian format irrespective of the register endian model.
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* So we put the value in little endian in memory, waiting
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* for fsl_edma_set_tcd_regs doing the swap.
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*/
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tcd->saddr = cpu_to_le32(src);
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tcd->daddr = cpu_to_le32(dst);
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tcd->attr = cpu_to_le16(attr);
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tcd->soff = cpu_to_le16(soff);
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tcd->nbytes = cpu_to_le32(nbytes);
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tcd->slast = cpu_to_le32(slast);
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tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer));
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tcd->doff = cpu_to_le16(doff);
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tcd->dlast_sga = cpu_to_le32(dlast_sga);
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tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter));
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if (major_int)
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csr |= EDMA_TCD_CSR_INT_MAJOR;
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if (disable_req)
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csr |= EDMA_TCD_CSR_D_REQ;
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if (enable_sg)
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csr |= EDMA_TCD_CSR_E_SG;
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tcd->csr = cpu_to_le16(csr);
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}
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static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
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int sg_len)
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{
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struct fsl_edma_desc *fsl_desc;
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int i;
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fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT);
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if (!fsl_desc)
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return NULL;
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fsl_desc->echan = fsl_chan;
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|
fsl_desc->n_tcds = sg_len;
|
|
for (i = 0; i < sg_len; i++) {
|
|
fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool,
|
|
GFP_NOWAIT, &fsl_desc->tcd[i].ptcd);
|
|
if (!fsl_desc->tcd[i].vtcd)
|
|
goto err;
|
|
}
|
|
return fsl_desc;
|
|
|
|
err:
|
|
while (--i >= 0)
|
|
dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd,
|
|
fsl_desc->tcd[i].ptcd);
|
|
kfree(fsl_desc);
|
|
return NULL;
|
|
}
|
|
|
|
struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
|
|
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
|
|
size_t period_len, enum dma_transfer_direction direction,
|
|
unsigned long flags)
|
|
{
|
|
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
|
struct fsl_edma_desc *fsl_desc;
|
|
dma_addr_t dma_buf_next;
|
|
int sg_len, i;
|
|
u32 src_addr, dst_addr, last_sg, nbytes;
|
|
u16 soff, doff, iter;
|
|
|
|
if (!is_slave_direction(direction))
|
|
return NULL;
|
|
|
|
if (!fsl_edma_prep_slave_dma(fsl_chan, direction))
|
|
return NULL;
|
|
|
|
sg_len = buf_len / period_len;
|
|
fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
|
|
if (!fsl_desc)
|
|
return NULL;
|
|
fsl_desc->iscyclic = true;
|
|
fsl_desc->dirn = direction;
|
|
|
|
dma_buf_next = dma_addr;
|
|
if (direction == DMA_MEM_TO_DEV) {
|
|
fsl_chan->attr =
|
|
fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
|
|
nbytes = fsl_chan->cfg.dst_addr_width *
|
|
fsl_chan->cfg.dst_maxburst;
|
|
} else {
|
|
fsl_chan->attr =
|
|
fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
|
|
nbytes = fsl_chan->cfg.src_addr_width *
|
|
fsl_chan->cfg.src_maxburst;
|
|
}
|
|
|
|
iter = period_len / nbytes;
|
|
|
|
for (i = 0; i < sg_len; i++) {
|
|
if (dma_buf_next >= dma_addr + buf_len)
|
|
dma_buf_next = dma_addr;
|
|
|
|
/* get next sg's physical address */
|
|
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
|
|
|
|
if (direction == DMA_MEM_TO_DEV) {
|
|
src_addr = dma_buf_next;
|
|
dst_addr = fsl_chan->dma_dev_addr;
|
|
soff = fsl_chan->cfg.dst_addr_width;
|
|
doff = 0;
|
|
} else {
|
|
src_addr = fsl_chan->dma_dev_addr;
|
|
dst_addr = dma_buf_next;
|
|
soff = 0;
|
|
doff = fsl_chan->cfg.src_addr_width;
|
|
}
|
|
|
|
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
|
|
fsl_chan->attr, soff, nbytes, 0, iter,
|
|
iter, doff, last_sg, true, false, true);
|
|
dma_buf_next += period_len;
|
|
}
|
|
|
|
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic);
|
|
|
|
struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
|
|
struct dma_chan *chan, struct scatterlist *sgl,
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
|
unsigned long flags, void *context)
|
|
{
|
|
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
|
struct fsl_edma_desc *fsl_desc;
|
|
struct scatterlist *sg;
|
|
u32 src_addr, dst_addr, last_sg, nbytes;
|
|
u16 soff, doff, iter;
|
|
int i;
|
|
|
|
if (!is_slave_direction(direction))
|
|
return NULL;
|
|
|
|
if (!fsl_edma_prep_slave_dma(fsl_chan, direction))
|
|
return NULL;
|
|
|
|
fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
|
|
if (!fsl_desc)
|
|
return NULL;
|
|
fsl_desc->iscyclic = false;
|
|
fsl_desc->dirn = direction;
|
|
|
|
if (direction == DMA_MEM_TO_DEV) {
|
|
fsl_chan->attr =
|
|
fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
|
|
nbytes = fsl_chan->cfg.dst_addr_width *
|
|
fsl_chan->cfg.dst_maxburst;
|
|
} else {
|
|
fsl_chan->attr =
|
|
fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
|
|
nbytes = fsl_chan->cfg.src_addr_width *
|
|
fsl_chan->cfg.src_maxburst;
|
|
}
|
|
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
/* get next sg's physical address */
|
|
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
|
|
|
|
if (direction == DMA_MEM_TO_DEV) {
|
|
src_addr = sg_dma_address(sg);
|
|
dst_addr = fsl_chan->dma_dev_addr;
|
|
soff = fsl_chan->cfg.dst_addr_width;
|
|
doff = 0;
|
|
} else {
|
|
src_addr = fsl_chan->dma_dev_addr;
|
|
dst_addr = sg_dma_address(sg);
|
|
soff = 0;
|
|
doff = fsl_chan->cfg.src_addr_width;
|
|
}
|
|
|
|
iter = sg_dma_len(sg) / nbytes;
|
|
if (i < sg_len - 1) {
|
|
last_sg = fsl_desc->tcd[(i + 1)].ptcd;
|
|
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
|
|
dst_addr, fsl_chan->attr, soff,
|
|
nbytes, 0, iter, iter, doff, last_sg,
|
|
false, false, true);
|
|
} else {
|
|
last_sg = 0;
|
|
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
|
|
dst_addr, fsl_chan->attr, soff,
|
|
nbytes, 0, iter, iter, doff, last_sg,
|
|
true, true, false);
|
|
}
|
|
}
|
|
|
|
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg);
|
|
|
|
void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
|
|
{
|
|
struct virt_dma_desc *vdesc;
|
|
|
|
lockdep_assert_held(&fsl_chan->vchan.lock);
|
|
|
|
vdesc = vchan_next_desc(&fsl_chan->vchan);
|
|
if (!vdesc)
|
|
return;
|
|
fsl_chan->edesc = to_fsl_edma_desc(vdesc);
|
|
fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd);
|
|
fsl_edma_enable_request(fsl_chan);
|
|
fsl_chan->status = DMA_IN_PROGRESS;
|
|
fsl_chan->idle = false;
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc);
|
|
|
|
void fsl_edma_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
|
|
|
if (unlikely(fsl_chan->pm_state != RUNNING)) {
|
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
|
/* cannot submit due to suspend */
|
|
return;
|
|
}
|
|
|
|
if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc)
|
|
fsl_edma_xfer_desc(fsl_chan);
|
|
|
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_edma_issue_pending);
|
|
|
|
int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
|
|
{
|
|
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
|
|
|
fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
|
|
sizeof(struct fsl_edma_hw_tcd),
|
|
32, 0);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources);
|
|
|
|
void fsl_edma_free_chan_resources(struct dma_chan *chan)
|
|
{
|
|
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
|
unsigned long flags;
|
|
LIST_HEAD(head);
|
|
|
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
|
fsl_edma_disable_request(fsl_chan);
|
|
fsl_edma_chan_mux(fsl_chan, 0, false);
|
|
fsl_chan->edesc = NULL;
|
|
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
|
|
fsl_edma_unprep_slave_dma(fsl_chan);
|
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
|
|
|
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
|
|
dma_pool_destroy(fsl_chan->tcd_pool);
|
|
fsl_chan->tcd_pool = NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources);
|
|
|
|
void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
|
|
{
|
|
struct fsl_edma_chan *chan, *_chan;
|
|
|
|
list_for_each_entry_safe(chan, _chan,
|
|
&dmadev->channels, vchan.chan.device_node) {
|
|
list_del(&chan->vchan.chan.device_node);
|
|
tasklet_kill(&chan->vchan.task);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan);
|
|
|
|
/*
|
|
* On the 32 channels Vybrid/mpc577x edma version (here called "v1"),
|
|
* register offsets are different compared to ColdFire mcf5441x 64 channels
|
|
* edma (here called "v2").
|
|
*
|
|
* This function sets up register offsets as per proper declared version
|
|
* so must be called in xxx_edma_probe() just after setting the
|
|
* edma "version" and "membase" appropriately.
|
|
*/
|
|
void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
|
|
{
|
|
edma->regs.cr = edma->membase + EDMA_CR;
|
|
edma->regs.es = edma->membase + EDMA_ES;
|
|
edma->regs.erql = edma->membase + EDMA_ERQ;
|
|
edma->regs.eeil = edma->membase + EDMA_EEI;
|
|
|
|
edma->regs.serq = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_SERQ : EDMA_SERQ);
|
|
edma->regs.cerq = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_CERQ : EDMA_CERQ);
|
|
edma->regs.seei = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_SEEI : EDMA_SEEI);
|
|
edma->regs.ceei = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_CEEI : EDMA_CEEI);
|
|
edma->regs.cint = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_CINT : EDMA_CINT);
|
|
edma->regs.cerr = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_CERR : EDMA_CERR);
|
|
edma->regs.ssrt = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_SSRT : EDMA_SSRT);
|
|
edma->regs.cdne = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_CDNE : EDMA_CDNE);
|
|
edma->regs.intl = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_INTL : EDMA_INTR);
|
|
edma->regs.errl = edma->membase + ((edma->drvdata->version == v2) ?
|
|
EDMA64_ERRL : EDMA_ERR);
|
|
|
|
if (edma->drvdata->version == v2) {
|
|
edma->regs.erqh = edma->membase + EDMA64_ERQH;
|
|
edma->regs.eeih = edma->membase + EDMA64_EEIH;
|
|
edma->regs.errh = edma->membase + EDMA64_ERRH;
|
|
edma->regs.inth = edma->membase + EDMA64_INTH;
|
|
}
|
|
|
|
edma->regs.tcd = edma->membase + EDMA_TCD;
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_edma_setup_regs);
|
|
|
|
MODULE_LICENSE("GPL v2");
|