![Luca Ceresoli](/assets/img/avatar_default.png)
When the DONE pin does not go high after programming to confirm programming success, the INIT_B pin provides some info on the reason. Use it if available to provide a more explanatory error message. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Moritz Fischer <mdf@kernel.org>
296 lines
6.7 KiB
C
296 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
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*
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* Copyright (C) 2017 DENX Software Engineering
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*
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* Anatolij Gustschin <agust@denx.de>
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*
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* Manage Xilinx FPGA firmware that is loaded over SPI using
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* the slave serial configuration interface.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/of.h>
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#include <linux/spi/spi.h>
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#include <linux/sizes.h>
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struct xilinx_spi_conf {
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struct spi_device *spi;
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struct gpio_desc *prog_b;
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struct gpio_desc *init_b;
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struct gpio_desc *done;
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};
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static int get_done_gpio(struct fpga_manager *mgr)
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{
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struct xilinx_spi_conf *conf = mgr->priv;
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int ret;
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ret = gpiod_get_value(conf->done);
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if (ret < 0)
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dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret);
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return ret;
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}
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static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
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{
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if (!get_done_gpio(mgr))
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return FPGA_MGR_STATE_RESET;
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return FPGA_MGR_STATE_UNKNOWN;
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}
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/**
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* wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
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* a given delay if the pin is unavailable
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*
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* @mgr: The FPGA manager object
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* @value: Value INIT_B to wait for (1 = asserted = low)
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* @alt_udelay: Delay to wait if the INIT_B GPIO is not available
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*
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* Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
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* too much time passed waiting for that. If no INIT_B GPIO is available
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* then always return 0.
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*/
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static int wait_for_init_b(struct fpga_manager *mgr, int value,
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unsigned long alt_udelay)
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{
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struct xilinx_spi_conf *conf = mgr->priv;
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unsigned long timeout = jiffies + msecs_to_jiffies(1000);
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if (conf->init_b) {
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while (time_before(jiffies, timeout)) {
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int ret = gpiod_get_value(conf->init_b);
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if (ret == value)
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return 0;
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if (ret < 0) {
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dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
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return ret;
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}
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usleep_range(100, 400);
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}
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dev_err(&mgr->dev, "Timeout waiting for INIT_B to %s\n",
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value ? "assert" : "deassert");
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return -ETIMEDOUT;
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}
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udelay(alt_udelay);
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return 0;
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}
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static int xilinx_spi_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct xilinx_spi_conf *conf = mgr->priv;
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int err;
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if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
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dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
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return -EINVAL;
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}
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gpiod_set_value(conf->prog_b, 1);
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err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
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if (err) {
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gpiod_set_value(conf->prog_b, 0);
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return err;
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}
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gpiod_set_value(conf->prog_b, 0);
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err = wait_for_init_b(mgr, 0, 0);
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if (err)
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return err;
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if (get_done_gpio(mgr)) {
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dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
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return -EIO;
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}
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/* program latency */
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usleep_range(7500, 7600);
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return 0;
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}
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static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf,
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size_t count)
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{
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struct xilinx_spi_conf *conf = mgr->priv;
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const char *fw_data = buf;
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const char *fw_data_end = fw_data + count;
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while (fw_data < fw_data_end) {
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size_t remaining, stride;
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int ret;
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remaining = fw_data_end - fw_data;
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stride = min_t(size_t, remaining, SZ_4K);
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ret = spi_write(conf->spi, fw_data, stride);
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if (ret) {
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dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
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ret);
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return ret;
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}
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fw_data += stride;
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}
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return 0;
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}
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static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf)
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{
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struct spi_device *spi = conf->spi;
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const u8 din_data[1] = { 0xff };
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int ret;
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ret = spi_write(conf->spi, din_data, sizeof(din_data));
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if (ret)
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dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret);
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return ret;
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}
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static int xilinx_spi_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct xilinx_spi_conf *conf = mgr->priv;
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unsigned long timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
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bool expired = false;
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int done;
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int ret;
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/*
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* This loop is carefully written such that if the driver is
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* scheduled out for more than 'timeout', we still check for DONE
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* before giving up and we apply 8 extra CCLK cycles in all cases.
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*/
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while (!expired) {
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expired = time_after(jiffies, timeout);
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done = get_done_gpio(mgr);
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if (done < 0)
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return done;
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ret = xilinx_spi_apply_cclk_cycles(conf);
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if (ret)
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return ret;
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if (done)
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return 0;
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}
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if (conf->init_b) {
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ret = gpiod_get_value(conf->init_b);
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if (ret < 0) {
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dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
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return ret;
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}
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dev_err(&mgr->dev,
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ret ? "CRC error or invalid device\n"
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: "Missing sync word or incomplete bitstream\n");
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} else {
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dev_err(&mgr->dev, "Timeout after config data transfer\n");
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}
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return -ETIMEDOUT;
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}
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static const struct fpga_manager_ops xilinx_spi_ops = {
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.state = xilinx_spi_state,
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.write_init = xilinx_spi_write_init,
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.write = xilinx_spi_write,
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.write_complete = xilinx_spi_write_complete,
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};
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static int xilinx_spi_probe(struct spi_device *spi)
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{
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struct xilinx_spi_conf *conf;
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struct fpga_manager *mgr;
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conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
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if (!conf)
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return -ENOMEM;
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conf->spi = spi;
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/* PROGRAM_B is active low */
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conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
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if (IS_ERR(conf->prog_b)) {
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dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n",
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PTR_ERR(conf->prog_b));
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return PTR_ERR(conf->prog_b);
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}
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conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
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if (IS_ERR(conf->init_b)) {
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dev_err(&spi->dev, "Failed to get INIT_B gpio: %ld\n",
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PTR_ERR(conf->init_b));
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return PTR_ERR(conf->init_b);
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}
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conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
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if (IS_ERR(conf->done)) {
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dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n",
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PTR_ERR(conf->done));
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return PTR_ERR(conf->done);
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}
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mgr = devm_fpga_mgr_create(&spi->dev,
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"Xilinx Slave Serial FPGA Manager",
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&xilinx_spi_ops, conf);
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if (!mgr)
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return -ENOMEM;
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spi_set_drvdata(spi, mgr);
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return fpga_mgr_register(mgr);
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}
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static int xilinx_spi_remove(struct spi_device *spi)
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{
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struct fpga_manager *mgr = spi_get_drvdata(spi);
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fpga_mgr_unregister(mgr);
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return 0;
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}
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static const struct of_device_id xlnx_spi_of_match[] = {
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{ .compatible = "xlnx,fpga-slave-serial", },
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{}
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};
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MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
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static struct spi_driver xilinx_slave_spi_driver = {
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.driver = {
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.name = "xlnx-slave-spi",
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.of_match_table = of_match_ptr(xlnx_spi_of_match),
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},
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.probe = xilinx_spi_probe,
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.remove = xilinx_spi_remove,
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};
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module_spi_driver(xilinx_slave_spi_driver)
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
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MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI");
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