![Borislav Petkov](/assets/img/avatar_default.png)
... into the global msr-index.h header because they're used in multiple compilation units. Sort the MSR list a bit. Update the msr-index.h copy in tools. No functional changes. Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://lkml.kernel.org/r/20200608164847.14232-1-bp@alien8.de
501 lines
12 KiB
C
501 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* fam15h_power.c - AMD Family 15h processor power monitoring
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*
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* Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
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* Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
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*/
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#include <linux/err.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/bitops.h>
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/time.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
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MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
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MODULE_LICENSE("GPL");
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/* D18F3 */
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#define REG_NORTHBRIDGE_CAP 0xe8
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/* D18F4 */
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#define REG_PROCESSOR_TDP 0x1b8
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/* D18F5 */
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#define REG_TDP_RUNNING_AVERAGE 0xe0
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#define REG_TDP_LIMIT3 0xe8
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#define FAM15H_MIN_NUM_ATTRS 2
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#define FAM15H_NUM_GROUPS 2
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#define MAX_CUS 8
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/* set maximum interval as 1 second */
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#define MAX_INTERVAL 1000
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#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
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struct fam15h_power_data {
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struct pci_dev *pdev;
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unsigned int tdp_to_watts;
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unsigned int base_tdp;
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unsigned int processor_pwr_watts;
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unsigned int cpu_pwr_sample_ratio;
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const struct attribute_group *groups[FAM15H_NUM_GROUPS];
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struct attribute_group group;
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/* maximum accumulated power of a compute unit */
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u64 max_cu_acc_power;
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/* accumulated power of the compute units */
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u64 cu_acc_power[MAX_CUS];
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/* performance timestamp counter */
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u64 cpu_sw_pwr_ptsc[MAX_CUS];
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/* online/offline status of current compute unit */
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int cu_on[MAX_CUS];
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unsigned long power_period;
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};
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static bool is_carrizo_or_later(void)
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{
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return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
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}
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static ssize_t power1_input_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 val, tdp_limit, running_avg_range;
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s32 running_avg_capture;
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u64 curr_pwr_watts;
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struct fam15h_power_data *data = dev_get_drvdata(dev);
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struct pci_dev *f4 = data->pdev;
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pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
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REG_TDP_RUNNING_AVERAGE, &val);
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/*
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* On Carrizo and later platforms, TdpRunAvgAccCap bit field
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* is extended to 4:31 from 4:25.
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*/
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if (is_carrizo_or_later()) {
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running_avg_capture = val >> 4;
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running_avg_capture = sign_extend32(running_avg_capture, 27);
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} else {
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running_avg_capture = (val >> 4) & 0x3fffff;
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running_avg_capture = sign_extend32(running_avg_capture, 21);
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}
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running_avg_range = (val & 0xf) + 1;
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pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
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REG_TDP_LIMIT3, &val);
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/*
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* On Carrizo and later platforms, ApmTdpLimit bit field
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* is extended to 16:31 from 16:28.
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*/
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if (is_carrizo_or_later())
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tdp_limit = val >> 16;
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else
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tdp_limit = (val >> 16) & 0x1fff;
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curr_pwr_watts = ((u64)(tdp_limit +
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data->base_tdp)) << running_avg_range;
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curr_pwr_watts -= running_avg_capture;
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curr_pwr_watts *= data->tdp_to_watts;
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/*
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* Convert to microWatt
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*
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* power is in Watt provided as fixed point integer with
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* scaling factor 1/(2^16). For conversion we use
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* (10^6)/(2^16) = 15625/(2^10)
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*/
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curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
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return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
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}
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static DEVICE_ATTR_RO(power1_input);
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static ssize_t power1_crit_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct fam15h_power_data *data = dev_get_drvdata(dev);
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return sprintf(buf, "%u\n", data->processor_pwr_watts);
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}
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static DEVICE_ATTR_RO(power1_crit);
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static void do_read_registers_on_cu(void *_data)
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{
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struct fam15h_power_data *data = _data;
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int cpu, cu;
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cpu = smp_processor_id();
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/*
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* With the new x86 topology modelling, cpu core id actually
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* is compute unit id.
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*/
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cu = cpu_data(cpu).cpu_core_id;
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rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
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rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
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data->cu_on[cu] = 1;
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}
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/*
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* This function is only able to be called when CPUID
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* Fn8000_0007:EDX[12] is set.
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*/
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static int read_registers(struct fam15h_power_data *data)
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{
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int core, this_core;
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cpumask_var_t mask;
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int ret, cpu;
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ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
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if (!ret)
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return -ENOMEM;
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memset(data->cu_on, 0, sizeof(int) * MAX_CUS);
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get_online_cpus();
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/*
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* Choose the first online core of each compute unit, and then
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* read their MSR value of power and ptsc in a single IPI,
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* because the MSR value of CPU core represent the compute
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* unit's.
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*/
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core = -1;
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for_each_online_cpu(cpu) {
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this_core = topology_core_id(cpu);
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if (this_core == core)
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continue;
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core = this_core;
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/* get any CPU on this compute unit */
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cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
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}
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on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);
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put_online_cpus();
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free_cpumask_var(mask);
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return 0;
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}
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static ssize_t power1_average_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct fam15h_power_data *data = dev_get_drvdata(dev);
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u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
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jdelta[MAX_CUS];
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u64 tdelta, avg_acc;
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int cu, cu_num, ret;
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signed long leftover;
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/*
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* With the new x86 topology modelling, x86_max_cores is the
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* compute unit number.
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*/
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cu_num = boot_cpu_data.x86_max_cores;
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ret = read_registers(data);
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if (ret)
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return 0;
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for (cu = 0; cu < cu_num; cu++) {
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prev_cu_acc_power[cu] = data->cu_acc_power[cu];
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prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
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}
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leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
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if (leftover)
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return 0;
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ret = read_registers(data);
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if (ret)
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return 0;
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for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
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/* check if current compute unit is online */
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if (data->cu_on[cu] == 0)
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continue;
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if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
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jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
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jdelta[cu] -= prev_cu_acc_power[cu];
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} else {
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jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
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}
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tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
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jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
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do_div(jdelta[cu], tdelta);
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/* the unit is microWatt */
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avg_acc += jdelta[cu];
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}
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return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
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}
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static DEVICE_ATTR_RO(power1_average);
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static ssize_t power1_average_interval_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct fam15h_power_data *data = dev_get_drvdata(dev);
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return sprintf(buf, "%lu\n", data->power_period);
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}
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static ssize_t power1_average_interval_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct fam15h_power_data *data = dev_get_drvdata(dev);
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unsigned long temp;
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int ret;
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ret = kstrtoul(buf, 10, &temp);
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if (ret)
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return ret;
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if (temp > MAX_INTERVAL)
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return -EINVAL;
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/* the interval value should be greater than 0 */
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if (temp <= 0)
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return -EINVAL;
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data->power_period = temp;
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return count;
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}
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static DEVICE_ATTR_RW(power1_average_interval);
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static int fam15h_power_init_attrs(struct pci_dev *pdev,
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struct fam15h_power_data *data)
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{
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int n = FAM15H_MIN_NUM_ATTRS;
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struct attribute **fam15h_power_attrs;
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struct cpuinfo_x86 *c = &boot_cpu_data;
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if (c->x86 == 0x15 &&
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(c->x86_model <= 0xf ||
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(c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
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n += 1;
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/* check if processor supports accumulated power */
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if (boot_cpu_has(X86_FEATURE_ACC_POWER))
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n += 2;
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fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
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sizeof(*fam15h_power_attrs),
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GFP_KERNEL);
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if (!fam15h_power_attrs)
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return -ENOMEM;
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n = 0;
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fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
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if (c->x86 == 0x15 &&
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(c->x86_model <= 0xf ||
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(c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
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fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
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if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
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fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
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fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
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}
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data->group.attrs = fam15h_power_attrs;
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return 0;
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}
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static bool should_load_on_this_node(struct pci_dev *f4)
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{
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u32 val;
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pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
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REG_NORTHBRIDGE_CAP, &val);
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if ((val & BIT(29)) && ((val >> 30) & 3))
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return false;
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return true;
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}
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/*
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* Newer BKDG versions have an updated recommendation on how to properly
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* initialize the running average range (was: 0xE, now: 0x9). This avoids
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* counter saturations resulting in bogus power readings.
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* We correct this value ourselves to cope with older BIOSes.
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*/
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static const struct pci_device_id affected_device[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
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{ 0 }
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};
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static void tweak_runavg_range(struct pci_dev *pdev)
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{
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u32 val;
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/*
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* let this quirk apply only to the current version of the
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* northbridge, since future versions may change the behavior
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*/
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if (!pci_match_id(affected_device, pdev))
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return;
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pci_bus_read_config_dword(pdev->bus,
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PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
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REG_TDP_RUNNING_AVERAGE, &val);
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if ((val & 0xf) != 0xe)
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return;
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val &= ~0xf;
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val |= 0x9;
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pci_bus_write_config_dword(pdev->bus,
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PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
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REG_TDP_RUNNING_AVERAGE, val);
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}
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#ifdef CONFIG_PM
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static int fam15h_power_resume(struct pci_dev *pdev)
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{
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tweak_runavg_range(pdev);
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return 0;
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}
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#else
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#define fam15h_power_resume NULL
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#endif
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static int fam15h_power_init_data(struct pci_dev *f4,
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struct fam15h_power_data *data)
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{
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u32 val;
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u64 tmp;
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int ret;
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pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
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data->base_tdp = val >> 16;
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tmp = val & 0xffff;
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pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
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REG_TDP_LIMIT3, &val);
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data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
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tmp *= data->tdp_to_watts;
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/* result not allowed to be >= 256W */
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if ((tmp >> 16) >= 256)
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dev_warn(&f4->dev,
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"Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
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(unsigned int) (tmp >> 16));
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/* convert to microWatt */
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data->processor_pwr_watts = (tmp * 15625) >> 10;
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ret = fam15h_power_init_attrs(f4, data);
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if (ret)
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return ret;
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/* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
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if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
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return 0;
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/*
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* determine the ratio of the compute unit power accumulator
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* sample period to the PTSC counter period by executing CPUID
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* Fn8000_0007:ECX
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*/
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data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
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if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
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pr_err("Failed to read max compute unit power accumulator MSR\n");
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return -ENODEV;
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}
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data->max_cu_acc_power = tmp;
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/*
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* Milliseconds are a reasonable interval for the measurement.
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* But it shouldn't set too long here, because several seconds
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* would cause the read function to hang. So set default
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* interval as 10 ms.
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*/
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data->power_period = 10;
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return read_registers(data);
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}
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static int fam15h_power_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct fam15h_power_data *data;
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struct device *dev = &pdev->dev;
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struct device *hwmon_dev;
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int ret;
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/*
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* though we ignore every other northbridge, we still have to
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* do the tweaking on _each_ node in MCM processors as the counters
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* are working hand-in-hand
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*/
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tweak_runavg_range(pdev);
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if (!should_load_on_this_node(pdev))
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return -ENODEV;
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data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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ret = fam15h_power_init_data(pdev, data);
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if (ret)
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return ret;
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data->pdev = pdev;
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data->groups[0] = &data->group;
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hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
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data,
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&data->groups[0]);
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return PTR_ERR_OR_ZERO(hwmon_dev);
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}
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static const struct pci_device_id fam15h_power_id_table[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
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{}
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};
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MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
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static struct pci_driver fam15h_power_driver = {
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.name = "fam15h_power",
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.id_table = fam15h_power_id_table,
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.probe = fam15h_power_probe,
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.resume = fam15h_power_resume,
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};
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module_pci_driver(fam15h_power_driver);
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